EP0432481A2
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EP
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Methods and apparatus for verifying the state of a plurality of electrically programmable memory cells
Assignee: Texas Instruments Inc
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Filing: 1990-11-13
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Granted: —
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Expires: 2010-11-13
Abstract
Abstract Apparatus for verifying the state of a plurality of electrically programmable memory cells (30-70) includes first and second memory cells (36, 38) each having current paths with first and second ends. A memory cell state sense node (BL2) is coupled to the first ends. A first array source node (82) is coupled to a second end of the current path of the first cell (36). A second array source node (84) is coupled to a second end of the current path of the second cell (38). First circuitry is provided for sensing a program verify state. Decoded ground circuitry couples a selected one of the first and second array source nodes to a low voltage source in response to the first circuitry sensing a program verify state. Second circuitry selectively isolates at least a nonselected one of the first and second array source nodes (82, 84) from the voltage bias source in response to the first circuitry sensing a program verify state.
Inventors
- 👤 John F. Schreck
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 13:04
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C16/10; G11C29/00; G11C29/04; G11C29/50; G11C16/04; G11C2029/5004
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
181 words
Apparatus for verifying the state of a plurality of electrically programmable memory cells, comprising: first and second memory cells, current paths of each of said cells having first and second ends, a memory cell state sense node coupled to said first ends; a first array source node coupled to said second end of said current path of said first cell; a second array source node coupled to said second end of said current path of said second cell; first circuitry for sensing a program verify state; decoded ground circuitry coupled to said first circuitry, and for selectively coupling a selected one of said first and second array source nodes to a low voltage source in response to said first circuitry sensing a program verify state; a voltage bias source having a voltage level substantially different from said low voltage source; and second circuitry coupled to said first circuitry, and for selectively isolating at least a nonselected one of said first and second array source nodes from said voltage bias source in response to said first circuitry sensing a program verify state.
Claim 2
Dependent Claim
54 words
The apparatus of Claim 1, wherein said first circuitry is operable to sense a read state different from said program verify state, said second circuitry coupling at least a nonselected one of said first and second array source nodes to said voltage bias source in response to said first circuitry sensing a read state.
Claim 3
Dependent Claim
35 words
The apparatus of Claim 1, wherein said second circuitry is operable to isolate all of said array source nodes from said voltage bias source in response to said first circuitry sensing a program verify state.
Claim 4
Dependent Claim
44 words
The apparatus of Claim 1, wherein said first and second memory cells each comprise an electrically programmable read only memory cell including a floating gate, a predetermined charge selectively impressed on said floating gates to render the current path of a respective cell nonconductive.
Claim 5
Dependent Claim
38 words
The apparatus of Claim 1, and further comprising a voltage bias source coupled to said bit line for providing a high voltage level to be sensed thereon in the instance that a selected cell has a zero state.
Claim 6
Dependent Claim
72 words
The apparatus of Claim 1, wherein said decoded ground circuitry comprises a transistor having a current path and a control electrode, said current path of said transistor selectively coupling one of said first and second array source nodes to a low voltage source having a voltage level less than said voltage bias source, a decoded ground signal selectively coupled to said control electrode of said transistor for rendering said current path conductive.
Claim 7
Dependent Claim
65 words
The apparatus of Claim 1, wherein said second circuitry comprises a transistor having a current path and a control electrode, said current path selectively coupling said nonselected one of said first and second array source nodes to a voltage bias source, said control electrode of said transistor having a voltage level impressed thereon during a program verify state sufficient to render said current path nonconductive.
Claim 8
Dependent Claim
113 words
The apparatus of Claim 7, wherein said transistor comprises a first p-channel field-effect transistor, said second circuitry further comprising a second p-channel field effect transistor having a current path for selectively coupling said voltage bias source to the control electrode of said first p-channel field effect transistor, a saturation signal having a low state and a high state, a gate of said second p-channel field effect transistor coupled to receive said saturation signal, a low state of said first program verify signal reducing the resistance of the current path of said second p-channel field effect transistor to couple the control electrode of said first p-channel field effect transistor to said voltage bias source.
Claim 9
Dependent Claim
114 words
The apparatus of Claim 1, wherein said decoded ground circuitry comprises an n-channel field effect transistor having a current path selectively coupling said selected one of said first and second array source nodes to said low voltage source, a gate of said n-channel field effect transistor for receiving a decoded ground signal, said second circuitry comprising a second n-channel field effect transistor having a current path for selectively coupling said voltage bias source to at least said non-selected one of said first and second array source nodes, a gate of said second n-channel field effect transistor receiving an inverse decoded ground signal for controlling the conductance of the current path of said second transistor.
Claim 10
Dependent Claim
215 words
An array of electrically programmable memory cells, comprising: a plurality of memory cells arranged in columns; for each of a plurality of pairs of columns, a bit line electrically disposed therebetween, first ends of current paths of cells in each said pair of columns coupled to said bit line; for each of a plurality of pairs of columns, an array source line electrically disposed therebetween, second ends of said current paths opposite said first ends of cells in each last said pair of columns coupled to said array source line; mode sensing circuitry for sensing a program verify mode; a plurality of array source driver circuits having outputs coupled to respective ones of said array source lines, each array source driver circuit coupled to said mode sensing circuitry, a voltage bias source and a low voltage source having a voltage level substantially different from the level of said voltage bias source, a selected one of said array source driver circuits coupling said low voltage source to a respective array source line in response to said mode sensing circuitry sensing a program verify mode, at least nonselected ones of said array source driver circuits isolating said voltage bias source from respective array source lines in response to said mode sensing circuitry sensing a program verify mode.
Claim 11
Dependent Claim
54 words
The array of Claim 10, wherein said mode sensing circuitry is further operable to sense a read mode different from said program verify mode, said nonselected ones of said array source driver circuits coupling said voltage bias source to respective array source lines in response to said mode sensing circuitry sensing a read mode.
Claim 12
Dependent Claim
38 words
The array of Claim 10, wherein each of said array source driver circuits is operable to isolate said voltage bias source from respective array source lines in response to said mode sensing circuitry sensing a program verify mode.
Claim 13
Dependent Claim
77 words
The array of Claim 10, wherein each of said memory cells is an electrically programmable read only memory cell, a floating gate of each said cell operable to have a predetermined charge programmed thereon, a control gate for impressing a predetermined read voltage thereon, said predetermined charge as programmed onto said floating gate rendering a said current path of a respective cell relatively nonconductive upon the impression of a said predetermined read voltage on said control gate.
Claim 14
Dependent Claim
91 words
The array of Claim 10, and further comprising a plurality of bias transistors, current paths of said bias transistors selectively coupling respective ones of said bit lines to a voltage bias source, a sense amplifier selectively coupled to each said bit line for reading a voltage level thereon, the voltage level of a selected bit line depending on the state of a selected memory cell to be read, a high voltage level on said selected bit line resulting from current from said bias transistor and current from a neighboring, nonselected cell.
Claim 15
Dependent Claim
48 words
The array of Claim 10, wherein each of said array source driver circuits includes a transistor having a current path for selectively connecting said respective array source line to said low voltage source, a control electrode of said transistor coupled to a source of a decoded ground signal.
Claim 16
Dependent Claim
86 words
The array of Claim 10, wherein said mode sensing circuitry comprises a first p-channel field effect transistor having a current path for coupling said voltage bias source to said respective array source line and a gate, a second p-channel field effect transistor having a current path for selectively coupling said voltage bias source to said gate of said first transistor, a gate of said second transistor coupled to a saturation signal, the voltage level of the saturation signal affecting the conductance of the current path thereof.
Claim 17
Dependent Claim
48 words
The array of Claim 10, wherein each said array source driver circuit comprises a transistor having a current path for selectively coupling said respective array source line to said voltage bias source, an inverse decoded ground signal coupled to a control electrode of said n-channel field effect transistor.
Claim 18
Independent Claim
138 words
A method for verifying the state of a plurality of electrically programmable memory cells, first ends of current paths of first and second memory cells coupled to a bit line, second ends of the current paths of said cells coupled to first and second array source nodes, each cell being read by sensing the state of the bit line while decoding the array source to be pulled to a low voltage level substantially different from a bias voltage level, the method comprising: sensing a program verify state; responsive to said step of sensing, coupling a selected one of first and second array source nodes to a source of the low voltage level; and responsive to said step of sensing, isolating at least a nonselected one of the first and second array source nodes from the voltage bias source.
Claim 19
Dependent Claim
50 words
The method of Claim 18, and further comprising the steps of: sensing a read state different from the program verify state; and responsive to said step of sensing the read state, coupling at least the nonselected one of the first and second array source nodes to the voltage bias source.
Claim 20
Dependent Claim
34 words
The method of Claim 18, and further comprising the step of isolating all of the array source nodes from the voltage bias source in response to said step of sensing a program verify state.
Claim 21
Dependent Claim
150 words
The method of Claim 18, and further comprising the steps of: determining that a selected one of the first and second memory cells is to be programmed to a "zero" state; impressing a programming voltage for a predetermined time on a control gate of the selected cell in order to cause an incremental amount of charge to exist on a floating gate of the selected cell; after said step of isolating, impressing a read voltage on the control gate of the selected cell; after sensing the voltage level of the selected bit line; determining whether the voltage level of the bit line is at a sufficiently high voltage level; and repeating said steps of programming, isolating, impressing a read voltage and sensing until sufficient charge has built up on the floating gate of the selected memory cell that at least a predetermined voltage level on the bit line is achieved.
Claim 22
Independent Claim
273 words
A method for programming an array of electrically programmable read only memory cells, the cells disposed in a plurality of pairs of columns each having a bit line therebetween, first ends of current paths of cells in each said column pair coupled to said respective bit line, a plurality of pairs of columns of the cells each having an array source line electrically disposed therebetween, for each of the last said pairs of columns, second ends of current paths of the cells opposed to said first ends coupled to said array source line such that each current path is selectrically disposed between a bit line and an array source line, the method comprising: if a selected memory cell is to be programmed to a "zero" state, addressing a selected memory cell; applying a programming pulse to a control gate of the addressed memory cell in order to cause a predetermined incremental amount of charge to reside on a floating gate of the cell; isolating at least nonselected ones of the array source lines from a voltage bias source; after said step of isolating, coupling a selected array source line adjacent the addressed cell to a low voltage source having a voltage level substantially different from the voltage bias source; sensing the voltage level of the bit line adjacent the selected memory cell; determining whether the voltage level of the selected bit line is at least as high as a predetermined voltage level; repeating said steps of applying a programming pulse, isolating, sensing and determining until a sufficiently high voltage level on the selected bit line is achieved; and selecting a next memory cell.
References Cited (Backward Citations)
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