EP0430707A2
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EP
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Extreme level circuit
Assignee: Toshiba Corp
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Filing: 1990-11-30
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Granted: —
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Expires: 2010-11-30
Abstract
Abstract An extreme level circuit for detecting an extreme level of two input signals. The circuit includes a differential circuit wherein a pair of differential transistors (T22, T23) are connected their emitters with each other and a common current source (IE11) is connected to the emitter junction node of the differential transistors (T22, T23), a pair of emitter follower transistors (T26, T27) coupled to the differential circuit for applying the input signals to the bases of the differential transistors (T26, T27) and a pair of bias generating circuits each coupled in series with one of the emitter follower circuits (T26, T27), wherein each bias generating circuit has a bias transistor (T24/T25) whose base being connected to a fixed bias source (VB2) and a current source (IE12/IE13) connected in series with the bias transistor (T24/T25), and wherein the pair of bias generating circuits are cross connected to the collectors of the differential transistors (T22, T23).
Inventors
- 👤 Toshikazu C/O Intellectual Property Div. Fujii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 05:39
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
200 words
An extreme level circuit for detecting an extreme level of two input signals, comprising a differential circuit including a pair of differential transistors (T22, T23; Q22, Q23; T22′, T23′) with their emitters connected together and a common current source (IE11; T11, R11; T11′, R11′) connected to the emitter junction node of the differential transistors (T22, T23; Q22, Q23; T22′, T23′) characterised in that the extreme level circuit further comprises: a pair of emitter follower transistors (T26, T27; Q26, Q27; T26′, T27′) coupled to the differential circuit for applying the input signals to the bases of the differential transistors (T22, T23; Q22, Q23; T22′, T23′); and a pair of bias generating circuit each coupled in series with one of the emitter follower transistors (T26, T27; Q26, Q27; T26′, T27′), wherein each bias generating circuit has a bias transistor (T24, T25; Q24, Q25; T24′, T25′) whose base is connected to a fixed bias source (VB2) and a current source (IE13, IE12; R13, R12; R13′, R12′) connected in series with the bias transistor (T24, T25; Q24, Q25; T24′, T25′); and wherein the pair of bias generating circuits are cross connected to the collectors of the differential transistors (T22, T23; Q22, Q23; T22′, T23′).
Claim 2
Dependent Claim
26 words
An extreme level circuit according to claim 1, wherein the current source in each of the bias generating circuits includes a resistor (R13, R12; R13′, R12′).
Claim 3
Dependent Claim
39 words
An extreme level circuit of claim 1, wherein the extreme level circuit includes bipolar transistors for the differential transistors (T22, T23; T22′, T23′), emitter follower transistors (T26, T27; T26′; T27′) and/or the bias generating transistors (T24, T25; T24′, T25′).
Claim 4
Dependent Claim
34 words
An extreme level circuit of claim 1, wherein the extreme level circuit includes field effect transistors for the differential transistors (Q22, Q23), emitter follower transistors (Q26, Q27) and/or the bias generating transistors (Q24, Q25).
Claim 5
Dependent Claim
334 words
An extreme level circuit for detecting an extreme level of two input signals, characterised in that the extreme level circuit comprises: a first differential circuit including a first differential transistor (T31) with its base connected to one of the input signals and a second differential transistor (T32), the emitters of the first and second differential transistors being connected together and a first current source (IE21) being connected between a first reference potential source (GND) and the emitter junction node of the first and second differential transistors (T31, T32); a first active load circuit (T33, T34; T45, T46) which is connected between a second reference potential source (Vcc) and the collectors of the first and second differential transistors (T31, T32) of the first differential circuit; a second differential circuit including a third differential transistor (T36) with its base connected to the other of the input signals and a fourth differential transistor (T37) with its base connected to the base of the second differential transistor (T32), the emitters of the third and fourth differential transistors being connected together and a second current source (IE22) being connected to the first reference potential source (GND) and to the emitter junction node of the third and fourth differential transistors (T36, T37); a second active load circuit (T38, T39) which is connected between the second reference potential source (Vcc) and the collectors of the third and fourth differential transistors (T36, T37) of the second differential circuit; a third current source (IE23) connected between the first reference potential source (GND) and the base junction node of the second and fourth differential transistors (T32, T37); a first feedback transistor (T35) having its base-emitter path connected in parallel with the collector-base path of the second differential transistor (T32) and its collector connected to the second reference potential source (Vcc); and a second feedback transistor (T40) having its base-emitter path connected in parallel with the collector-base path of the fourth differential transistor (T37) and its collector connected to the second reference potential source (Vcc).
Claim 6
Dependent Claim
91 words
An extreme level circuit according to claim 5, further comprising: a first cross feedback transistor (T42) with its base connected to the base of the first feedback transistor (T35) and its collector-emitter path connected between the second reference potential source (Vcc) and the collector of the fourth differential transistor (T37); and a second cross feedback transistor (T44) with its base connected to the base of the second feedback transistor (T40) and its collector-emitter path connected between the second reference potential source (Vcc) and the collector of the second differential transistor (T32).
Claim 7
Dependent Claim
27 words
An extreme level circuit according to claim 5 or 6, wherein each of the first and second active load circuits includes a current mirror circuit (T33, T34).
Claim 8
Dependent Claim
36 words
An extreme level circuit according to claim 5 or 6, wherein each of the first and second active load circuits includes a bias transistor (T45, T46) with its base connected to a fixed bias source (VB4).
References Cited (Backward Citations)
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