EP0430086A2
Expired / Lapsed
EP
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Hetero junction bipolar transistor and its manufacturing method
Assignee: Hitachi Ltd
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Filing: 1990-11-22
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Granted: —
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Expires: 2010-11-22
Abstract
Abstract A hetero junction bipolar transistor has an area of contact between an emitter (or collector) electrode (6) and a wiring (13) formed on the electrode (6) which is larger than the area of the emitter (or collector) (5). A variation in voltage applied to the emitter (or collector)-base junction is prevented and stable operation of the transistor is attained. In addition, when an etching operation is carried out, an insulation film is formed on a side part of a mask, a patterning of the emitter (or collector) is carried out and thus trouble caused by the side etching is reduced and an emitter (or collector) having a size approximate to that of the mask is formed.
Inventors
- 👤 Chushiroh San-Kohpo Kusano
- 👤 Hiroshi Masuda
- 👤 Katsuhiko Mitani
- 👤 Kazuhiro Mochizuki
- 👤 Masaru Miyazaki
- 👤 Masahiko Kawata
- 👤 Susumu Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 10:05
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/80; H10D10/821; H10D62/00; H10D62/10; H10D62/13; H10D62/133; H10D62/136; H10D62/137
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
171 words
A hetero junction bipolar transistor comprising a semi-insulative compound semiconductor substrate (1), at least a first compound semiconductor layer (2) having a first conductivity type formed on said substrate (1), a second compound semiconductor layer (3) having a second conductivity type opposite to said first conductivity type formed on said first semiconductor layer (2) and having a predetermined shape, a third compound semiconductor layer (4) having said first conductivity type formed on said second semiconductor layer (3) and having a desired shape composed of material differing from that of said second semiconductor layer (3), a fourth compound semiconductor layer (5) having said first conductivity type formed on said third semiconductor layer (4) and having a desired shape composed of material differing from said third semiconductor layer (4), an electrode (6) formed on said fourth semiconductor layer (5) and a wiring (13) formed on said electrode (6), wherein the area of contact between said electrode (6) and said wiring (13) is no smaller than the area of said fourth semiconductor layer (5).
Claim 2
Dependent Claim
21 words
The transistor of claim 1, wherein a low-resistance compound semiconductor layer is disposed between said first semiconductor layer and said substrate.
Claim 3
Dependent Claim
21 words
The transistor of claim 1 or 2, wherein a low-resistance layer is interposed between said fourth semiconductor layer and said electrode.
Claim 4
Dependent Claim
19 words
The transistor of any of claims 1 to 3 and formed as an emitter-top type hetero junction bipolar transistor.
Claim 5
Dependent Claim
33 words
The transistor of claim 4, wherein said first semiconductor layer (2) is a collector, said second semiconductor layer (3) is a base and said third and fourth semiconductor layers (4, 5) are emitters.
Claim 6
Dependent Claim
21 words
The transistor of any of claims 1 to 5, wherein said first and second conductivity types are n-type and p-type, respectively.
Claim 7
Dependent Claim
23 words
The transistor of any of claims 1 to 6, wherein said first, second and fourth semiconductor layers (2, 3, 5) are of GaAs.
Claim 8
Dependent Claim
18 words
The transistor of any of claims 1 to 7, wherein said third semiconductor layer (4) is of GaAℓAs.
Claim 9
Dependent Claim
31 words
The transistor of any of claims 1 to 8, wherein areas of said third and fourth semiconductor layers (4, 5) are smaller than an area of said second semiconductor layer (3).
Claim 10
Dependent Claim
46 words
The transistor of any of claims 5 to 9, wherein a side wall of said emitter (4, 5) is formed with an insulation film (8), and a second electrode (9) in contact with said insulation film (8) is formed on a surface of said base (3).
Claim 11
Dependent Claim
46 words
The transistor of any of claims 5 to 9, wherein said collector (2) has a mesa portion and a lower part adjacent to this mesa portion, said base (3) being formed on said mesa portion, and a third electrode (10) being formed on said lower portion.
Claim 12
Dependent Claim
168 words
A hetero junction bipolar transistor comprising a semi-insulative compound semiconductor substrate (14), at least a first compound semiconductor layer (15) having a first conductivity type formed on said substrate (14), a second compound semiconductor layer (16) having said first conductivity type formed on said first semiconductor layer (15) and made of material differing from that of said first semiconductor layer (15), a third compound semiconductor layer (17) having a second conductivity type opposite to said first conductivity type formed on said second semiconductor layer (16) and having a desired shape composed of material differing from that of said second semiconductor layer (16), a fourth compound semiconductor layer (18) formed on said third semiconductor layer (17), having said first conductivity type and having a desired shape, an electrode (25) formed on said fourth semiconductor layer (18), and a wiring (27) formed on said electrode (25), wherein the area of contact between said electrode (25) and said wiring (27) is larger than the area of said fourth semiconductor layer (18).
Claim 13
Dependent Claim
15 words
The transistor of claim 12 and formed as a collector-top type hetero junction bipolar transistor.
Claim 14
Dependent Claim
29 words
The transistor of claim 13, wherein said first and second semiconductor layers are emitters, said third semiconductor layer is a base and said fourth semiconductor layer is a collector.
Claim 15
Dependent Claim
25 words
The transistor of any of claims 1 to 14, wherein the entire surface of said electrode (6; 25) is covered by said wiring (13; 27).
Claim 16
Independent Claim
243 words
A method for manufacturing a hetero junction bipolar transistor comprising the steps of: accumulating in sequence on a main surface of a semi-insulative compound semiconductor substrate (1) a first compound semiconductor (2) having a first conductivity type, a second compound semiconductor layer (3) having a second conductivity type opposite to said first conductivity type, a third compound semiconductor layer (4) having said first conductivity type and composed of material differing from said second semiconductor layer (3), and a fourth compound semiconductor layer (5) having said first conductivity type and composed of material differing from that of said third semiconductor layer (4); forming an emitter pattern (6) having a predetermined shape on said fourth semiconductor layer (5); forming an insulation film (8') on a side of said emitter pattern (6); etching the exposed portions of said fourth and third semiconductor layers (5, 4) to remove them by using said emitter pattern (6) and said insulating film (8) as a mask, and removing said insulation film (8'); etching the exposed portions of said second and first semiconductor layers (3, 2) by using a larger mask than said emitter pattern (6); forming an electrode electrically connected with an upper surface of said fourth semiconductor layer (5) and having a larger area than that of said fourth semiconductor layer (5); forming a conductive film (13) over the entire surface; and removing the non-required portion of said conductive film (13) to form a wiring connected to said electrode.
Claim 17
Dependent Claim
16 words
The method of claim 16, wherein said electrode is formed after removing said emitter pattern (6).
Claim 18
Dependent Claim
17 words
The method of claim 16, wherein said electrode is formed without removing of said emitter pattern (6).
References Cited (Backward Citations)
No citation records indexed.
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