EP0427023A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data transmission control apparatus for parallel processing system
Assignee: Fujitsu Ltd
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Filing: 1990-10-18
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Granted: —
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Expires: 2010-10-18
Abstract
Abstract Data transmission control apparatus which controls data transmission between processing systems (1) via a transmission line (2), each processing system (1) including a memory system consisting of a main memory (12) and a cache memory (11). The apparatus addresses data in the memory system by a memory address and gives an instruction to transmit the addressed data; judges whether or not the addressed data is in the cache memory (11), and, when the data is in the cache memory (11), provides a match signal; when instructed by said instruction and a ready signal is provided, reads the addressed data from the cache memory (11) if the match signal is provided and, otherwise, from said main memory (12), and writes the read data into a port (13); which transmits the data written therein to the other processing system (1) connected to the transmission line (2) and provides the ready signal when it is ready to write the next data therein.
Inventors
- 👤 Toshiyuki Shimizu
- 👤 Hiroaki Ishihata
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 12:17
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0813; G06F12/0804; G06F15/00; G06F15/16; G06F15/163; G06F15/173
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
173 words
Data transmission control apparatus which controls data transmission between processing systems (1) via a transmission line (2), each processing system including a memory system consisting of a main memory (12) and a cache memory (11), said apparatus comprising: instruction means (14, 17) for addressing data in said memory system by a memory address and for giving an instruction to transmit the addressed data; transmission means (13), connected to said transmission line (2), for transmitting the data written therein to said other processing system and for providing a ready signal when it is ready to write the next data therein; judgement means (18) for judging that the data addressed by said instruction means is in said cache memory (11) and for providing a match signal thereupon; and transfer means for acknowledging the ready signal and, based on the ready signal, for reading the addressed data from said cache memory (11) when the match signal is provided and, otherwise, from said main memory (12), and for writing the read data into said transmission menas (13).
Claim 2
Dependent Claim
173 words
Data transmission control apparatus which controls data transmission between processing systems (1) via a transmission line (2), each processing system including a memory system consisting of a main memory (12) and a cache memory (11), said apparatus comprising: instruction means (14, 17) for addressing data in said memory system by a memory address and for giving an instruction to transmit the addressed data; transmission means (13), connected to said transmission line (2), for transmitting the data written therein to said other processing system and for providing a ready signal when it is ready to write the next data therein; judgement means (18) for judging that the data addressed by said instruction means is in said cache memory (11) and for providing a match signal thereupon; and transfer means for acknowledging the ready signal and, based on the ready signal, for reading the addressed data from said cache memory (11) when the match signal is provided and, otherwise, from said main memory (12), and for writing the read data into said transmission menas (13).
Claim 3
Dependent Claim
67 words
Data transmission control apparatus according to claim 1, wherein said judgement means (18) includes a memory means for storing the main memory address bits for the data stored in said cache memory (11) and a means for comparing the contents of said memory means on a bit-by-bit basis with the main memory address bits given by said processor (10), to provide the match signal on a match.
Claim 4
Dependent Claim
110 words
Data transmission control apparatus according to claim 1 or 2, wherein the main memory address bits constitute a first part and a second part, and wherein said judgement means (18) includes a memory means for storing a first part of the main memory address bits for te data stored in said cache memory (11), a means for accessing said memory means by a second part of remaining main memory address bits and a means for comparing the contents of said memory means on a bit-by-bit basis with the said first part of the main memory address bits given by said processor (10), to provide the match signal on a match.
Claim 5
Dependent Claim
50 words
Data transmission control apparatus according to anyone of claims 1 to 3, wherein said instruction means includes a particular operation code which gives an instruction to transmit the addressed data and further comprising a decoder means (17) for decoding said operation code to instruct said transfer means to transfer data.
Claim 6
Dependent Claim
48 words
Data transmission control apparatus according to anyone of claims 1 to 3, wherein an address part of said instruction means gives an instruction to transmit the addressed data, and further comprising a decoder means (17) for decoding the address part to instruct said transfer means to transfer data.
Claim 7
Dependent Claim
77 words
Data transmission control apparatus according to anyone of claims 1 to 3, wherein said instruction means includes an address part consisting of a first part and a second part, the first part giving an instruction to transmit the addressed data and the second part designating a main memory address where the data to be transmitted is stored, and further comprising a decoder means (17) for decoding the first part to instruct said transfer means to transfer data.
Claim 8
Dependent Claim
98 words
Data transmission control apparatus according to anyone of claims 1 to 3, wherein said instruction means consists of an instruction to store a register with a main memory address where the data to be transmitted is stored and an instruction whose address part includes a particular code giving an instruction to transmit the addressed data, and further comprising a decoder means (17) for decoding the address part to detect said particular code and a selection means for selecting the contents of the register as a main memory address based on said particular code detected by said decoder means.
Claim 9
Dependent Claim
123 words
Data transmission control apparatus which controls data transmission between processing systems (1) via a transmission line (2), each processing system including a main memory (12), said apparatus comprising: instruction means (14, 17) for addressing data in said main memory (12) by a memory address and for giving an instruction to transmit the addressed data; transmission means (13), connected to said transmission line (2), for transmitting the data written therein to said other processing system (1) and for providing a ready signal when it is ready to write the next data therein; transfer means for acknowledging the ready signal and, based on the ready signal, for reading the addressed data from said main memory and for writing the read data into said transmission means.
Claim 10
Dependent Claim
123 words
Data transmission control apparatus which controls data transmission between processing systems (1) via a transmission line (2), each processing system including a main memory (12), said apparatus comprising: instruction means (14, 17) for addressing data in said main memory (12) by a memory address and for giving an instruction to transmit the addressed data; transmission means (13), connected to said transmission line (2), for transmitting the data written therein to said other processing system (1) and for providing a ready signal when it is ready to write the next data therein; transfer means for acknowledging the ready signal and, based on the ready signal, for reading the addressed data from said main memory and for writing the read data into said transmission means.
Claim 11
Dependent Claim
47 words
Data transmission control apparatus according to claim 8, wherein said instruction means (14, 17) includes a particular operation code which gives an instruction to transmit the addressed data and further comprising a decoder means for decoding said operation code to instruct said transfer means to transfer data.
Claim 12
Dependent Claim
46 words
Data transmission control apparatus according to claim 8, wherein an address part of said instruction means (14, 17) gives an instruction to transmit the addressed data, and further comprising a decoder means (17) for decoding the address part to instruct said transfer means to transfer data.
Claim 13
Dependent Claim
75 words
Data transmission control apparatus according to claim 8, wherein said instruction means (14, 17) includes an address part consisting of a first part and a second part, the first part giving an instruction to transmit the addressed data and the second part designating a main memory address where the data to be transmitted is stored, and further comprising a decoder means (17) for decoding the first part to instruct said transfer means to transfer data.
Claim 14
Dependent Claim
97 words
Data transmission control apparatus according to claim 8, wherein said instruction means (14, 17) consists of an instruction to store a register with a main memory address where the data to be transmitted is stored and an instruction whose address part includes a particular code giving an instruction to transmit the addressed data, and further comprising a decoder means (17) for decoding the address part to detect said particular code and a selection means for selecting the contents of the register as a main memory address based on said particular code detected by said decoder means (17).
References Cited (Backward Citations)
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