EP0424926A2
Expired / Lapsed
EP
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Bi-CMOS integrated circuit
Assignee: Toshiba Corp
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Filing: 1990-10-24
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Granted: —
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Expires: 2010-10-24
Abstract
Abstract There is disclosed a Bi-CMOS integrated circuit including an NPN-type (8, 15, 16) bipolar transistor, a P-MOS transistor (9, 17, 20), an N-MOS transistor (11, 18, 21) which are formed on the same substrate, wherein an N-type region (1, 2, 4, 9) is formed so that a P-type isolation region for isolating the NPN-type bipolar transistor and the MOS transistor is electrically isolated from the P-type region for the N-MOS transistor. In such a structure, since different bias potentials can be applied to the P-type isolation region and the P-type region for the N-MOS transistor, respectively, high speed operation can be attained without any erroneous operation.
Inventors
- 👤 Hideki Yamada
- 👤 Makoto Segawa
- 👤 Kiminobu Suzuki
- 👤 Kiyoshi Kobayashi
- 👤 Shigeto Mizukami
- 👤 Yasumitsu Nozawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 12:55
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/01; H10D84/0107; H10D84/0109
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
90 words
A Bi-CMOS integrated circuit comprising: an NPN transistor (8, 15, 16) formed on a substrate surface, and a CMOS transistor comprised of a P-channel MOS transistor (9, 17, 20) and an N-channel MOS transistor, (11, 18, 21) formed on said substrate surface, and characterized in that said circuit further comprises an N-type region (1, 2, 4, 9) for isolation for electrically isolating a P-type region for isolation between bipolar/CMOS adjoining an N-type region serving as the collector of said NPN transistor and a P-type region of said P-channel MOS transistor.
Claim 2
Dependent Claim
90 words
A Bi-CMOS integrated circuit comprising: an NPN transistor (8, 15, 16) formed on a substrate surface, and a CMOS transistor comprised of a P-channel MOS transistor (9, 17, 20) and an N-channel MOS transistor, (11, 18, 21) formed on said substrate surface, and characterized in that said circuit further comprises an N-type region (1, 2, 4, 9) for isolation for electrically isolating a P-type region for isolation between bipolar/CMOS adjoining an N-type region serving as the collector of said NPN transistor and a P-type region of said P-channel MOS transistor.
Claim 3
Dependent Claim
38 words
A Bi-CMOS integrated circuit as set forth in claim 1, wherein said N-type region for isolation is comprised of an N-type substrate (1) and an N-type region (9) of said P-channel MOS transistor provided on the surface thereof.
Claim 4
Dependent Claim
80 words
A Bi-CMOS integrated circuit as set forth in claim 1, wherein said NPN transistor and said CMOS transistor are formed within a P-type epitaxial layer (7) formed on the surface of an N-type substrate, and wherein said N-type region for isolation is comprised of said N-type substrate, an N-type well formed within said p-type epitaxial layer on the surface of said N-type substrate, and an N-type region for said P-channel MOS transistor formed within a P-type epitaxial layer formed thereon.
Claim 5
Dependent Claim
39 words
A Bi-CMOS integrated circuit as set forth in claim 3, wherein an N-type buried layer (2) is provided between said N-type substrate and an N well formed within said P-type epitaxial layer on the surface of said N-type substrate.
Claim 6
Dependent Claim
42 words
A Bi-CMOS integrated circuit as set forth in claim 1, wherein said N-type region for isolation is composed of an N-type substrate (1) and an N-type trench region (30) formed so that its bottom portion is in contact with said N-type substrate.
Claim 7
Dependent Claim
38 words
A Bi-CMOS integrated circuit as set forth in claim 1, wherein different bias voltages are applied to said N-type region serving as said collector of said NPN transistor and said P-type region of said P-channel MOS transistor, respectively.
Claim 8
Dependent Claim
26 words
A Bi-CMOS integrated circuit as set forth in claim 6, wherein bias generation means (40) for generating different bias voltages is provided on the same chip.
References Cited (Backward Citations)
No citation records indexed.
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