EP0424741A2
Expired / Lapsed
EP
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Method and structure for digital phase synchronization
Assignee: National Semiconductor Corp
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Filing: 1990-10-11
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Granted: —
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Expires: 2010-10-11
Abstract
Abstract A plurality of delay means are used to provide a plurality of delayed input signals, which are then compared with the receiver clock signal in order to determine which of the delayed input signals is closest in phase to the receiver clock signal. Once this determination is made, a multiplexer is used to select the appropriate one of the plurality of delayed input signals for use by the receiver. In an alternative embodiment, a plurality of delay means are used to provide a plurality of delayed clock signals, which are then compared with the receiver input signal in order to determine which of the delayed clock signals is closest in phase to the receiver input signal. Once this determination is made, a multiplexer is used to select the appropriate one of the plurality of delayed clock signals for use by the receiver.
Inventors
- 👤 Richard Dean Henderson
- 👤 Frederick Kwok Ying Leung
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 06:17
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/0338; H04L7/04; H04L7/041; H04L7/044
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
154 words
A phase synchronization circuit comprising: an input port for receiving an input signal; a clock input lead for receiving a clock signal; a plurality of N delay means for providing a plurality of delayed input signals in response to said input signal; a plurality of N phase detector means, each having an input lead connected to receive an associated one of said delayed input signals, a clock input lead for receiving said clock signal, and an output signal for providing an indication of the phase relation between its associated one of said delayed input signals and said clock signal; decoder means for receiving said output signals from said phase detector means and in response thereto determining which one of said delayed input signals has a desired phase relationship with said clock signal; and selector means for selecting said one of said delayed input signals which has said desired phase relationship with said clock signal.
Claim 2
Dependent Claim
154 words
A phase synchronization circuit comprising: an input port for receiving an input signal; a clock input lead for receiving a clock signal; a plurality of N delay means for providing a plurality of delayed input signals in response to said input signal; a plurality of N phase detector means, each having an input lead connected to receive an associated one of said delayed input signals, a clock input lead for receiving said clock signal, and an output signal for providing an indication of the phase relation between its associated one of said delayed input signals and said clock signal; decoder means for receiving said output signals from said phase detector means and in response thereto determining which one of said delayed input signals has a desired phase relationship with said clock signal; and selector means for selecting said one of said delayed input signals which has said desired phase relationship with said clock signal.
Claim 3
Dependent Claim
27 words
A phase synchronization circuit as in claim 1 wherein said selector means comprises a 1 of N selector, where N is the number of delayed input signals.
Claim 4
Dependent Claim
53 words
A phase synchronization circuit as in claim 1 wherein said delay means are connected in series such that the delayed input signal provided by a selected one of said delay means is delayed by an amount equal to the sum of said selected delay means plus the delays provided by preceding delay means.
Claim 5
Dependent Claim
151 words
A phase synchronization circuit comprising: an input port for receiving an input signal; a clock input lead for receiving a clock signal; a plurality of delay means for providing a plurality of delayed clock signals in response to said clock signal; a plurality of phase detector means, each having a clock input lead connected to receive an associated one of said delayed clock signals, an input lead for receiving said input signal, and an output signal for providing an indication of the phase relation between its associated one of said delayed clock signals and said input signal; decoder means for receiving said output signals from said phase detector means and in response thereto determining which one of said delayed clock signals has a desired phase relationship with said input signal; and selector means for selecting said one of said delayed clock signals has said desired phase relationship with said input signal.
Claim 6
Dependent Claim
151 words
A phase synchronization circuit comprising: an input port for receiving an input signal; a clock input lead for receiving a clock signal; a plurality of delay means for providing a plurality of delayed clock signals in response to said clock signal; a plurality of phase detector means, each having a clock input lead connected to receive an associated one of said delayed clock signals, an input lead for receiving said input signal, and an output signal for providing an indication of the phase relation between its associated one of said delayed clock signals and said input signal; decoder means for receiving said output signals from said phase detector means and in response thereto determining which one of said delayed clock signals has a desired phase relationship with said input signal; and selector means for selecting said one of said delayed clock signals has said desired phase relationship with said input signal.
Claim 7
Dependent Claim
21 words
A phase synchronization circuit as in claim 1 or 4 wherein said phase detector means each comprise a D flip flop.
Claim 8
Dependent Claim
45 words
A phase synchronization circuit as in claim 1 or 4 wherein said decoder means comprises a plurality of exclusive OR gates, each of said exclusive OR gates having a first input lead connected to receive the output signals of two of said phase detector means.
Claim 9
Dependent Claim
27 words
A phase synchronization circuit as in claim 4 wherein said selector means comprises a 1 of N selector where N is the number of delayed clock signals.
Claim 10
Dependent Claim
53 words
A phase synchronization circuit as in claim 4 wherein said delay means are connected in series such that the delayed clock signal provided by a selected one of said delay means is delayed by an amount equal to the sum of said selected delay means plus the delays provided by preceding delay means.
Claim 11
Dependent Claim
22 words
A phase synchronization circuit as in claim 3 or 8 wherein said plurality of delay means each provide approximately the same delay.
Claim 12
Dependent Claim
24 words
A phase synchronization circuit as in claim 3 or 8 wherein said plurality of delay means do not each provide approximately the same delay.
Claim 13
Dependent Claim
19 words
A phase synchronization circuit as in claim 1 or 4 which further comprises detection means comprising a storage element.
Claim 14
Independent Claim
96 words
A method for phase synchronization comprising the steps of: receiving an input signal carrying data at a specified frequency; providing a plurality of delayed input signals in response to said input signal, each of said delayed input signals being delayed from said input signal by an associated period of time; receiving a clock signal of said specified frequency; selecting the one of said plurality of delayed input signals that has a desired phase relationship with said clock signal; and using said selected one of said delayed input signals to detect said data on said input signal.
Claim 15
Independent Claim
96 words
A method for phase synchronization comprising the steps of: receiving an input signal carrying data at a specified frequency; providing a plurality of delayed input signals in response to said input signal, each of said delayed input signals being delayed from said input signal by an associated period of time; receiving a clock signal of said specified frequency; selecting the one of said plurality of delayed input signals that has a desired phase relationship with said clock signal; and using said selected one of said delayed input signals to detect said data on said input signal.
Claim 16
Dependent Claim
75 words
A method as in claim 12 wherein said step of using said selected one of said delayed input signals to detect said data on said input signal comprises the step of using said selected delayed input signal to cause the approximate center of a data bit in said selected delayed input signal to correspond to a selected edge of said clock signal at which sampling of said data in said selected delayed input signal occurs.
Claim 17
Independent Claim
96 words
A method for phase synchronization comprising the steps of: receiving an input signal carrying data at a specified frequency; receiving a clock signal of said specified frequency; providing a plurality of delayed clock signals in response to said clock signal, each of said delayed clock signals being delayed from said clock signal by an associated period of time; selecting the one of said plurality of delayed clock signals that has a desired phase relationship with said input signal; and using said selected one of said delayed clock signals to detect said data on said input signal.
Claim 18
Independent Claim
96 words
A method for phase synchronization comprising the steps of: receiving an input signal carrying data at a specified frequency; receiving a clock signal of said specified frequency; providing a plurality of delayed clock signals in response to said clock signal, each of said delayed clock signals being delayed from said clock signal by an associated period of time; selecting the one of said plurality of delayed clock signals that has a desired phase relationship with said input signal; and using said selected one of said delayed clock signals to detect said data on said input signal.
Claim 19
Dependent Claim
43 words
A method as in claim 12 or 14 wherein said one of said delayed input signals which has said desired phase relationship with said clock signal is the one of said delayed input signals which is closest in phase to said clock signal.
Claim 20
Dependent Claim
73 words
A method as in claim 14 wherein said step of using said selected one of said delayed clock signals to detect said data on said input signal comprises the step of using said selected delayed clock signal to cause the approximate center of a data bit in said input signal to correspond to a selected edge of said selected delayed clock signal at which sampling of said data in said input signal occurs.
References Cited (Backward Citations)
No citation records indexed.
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