EP0423979A2
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EP
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High definition video signal recording systems
Assignee: Sony Corp
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Filing: 1990-10-04
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Granted: —
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Expires: 2010-10-04
Abstract
Abstract A system is provided for recording one or more individual fields or frames of a colour, high definition video (HDTV) signal. The system has a memory unit (40 - Figures 1C and 1D) that is capable of digitally recording as many as 32 frames of a colour HDTV signal per memory board (42, 44, 46, 48) thereof, and as many as four memory boards may be installed in the system. The system is capable of performing partial or full frame (or field) transfers at any selected rate less than or equal to the standard video rate. The system accepts HDTV signals in either digital or analog format, and includes a post processor (60 - Figure 1E) for simultaneously reconstructing stored HDTV signals in both digital and analog format, and a control unit (80 - Figure 1B) which emulates a conventional video tape recorder (in the sense that it responds to conventional video tape recorder control signals) for controlling the memory unit (40). A parallel computer interface permits transfer of full or partial fields or frames (in non-real time) between the memory unit (40) and an external computer (or image processing unit) via a conventional communication link. The control unit (80) and an interface unit (100) including the parallel computer interface are connected by a serial communications link, so that a host computer may control memory access through the interface unit (100).
Inventors
- 👤 Vinson R. Perry
- 👤 Marc Klingelhofer
- 👤 Thomas A. Rohwer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 12:18
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N5/00; H04N5/76; H04N5/91; H04N9/797
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
156 words
A high definition video signal recording system, including: a frame memory unit (40) for receiving parallel format data representing a high definition video signal, the frame memory unit including memory circuitry capable of storing data representing one or more frames of the high definition video signal; an interface unit (100) including a parallel interface means for communicating with an external processing system; a parallel communications link for transferring parallel format high definition video data between the interface unit (100) and the frame memory unit (40); and a control unit (80) connected to the frame memory unit (40) and the interface unit (100), for controlling the transfer of parallel format data representing high definition video signal frames or fields into storage within the frame memory unit (40), and for controlling the transfer of stored data representing high definition video frames or fields from the memory circuitry within the frame memory unit (40) to the parallel communications link.
Claim 2
Dependent Claim
156 words
A high definition video signal recording system, including: a frame memory unit (40) for receiving parallel format data representing a high definition video signal, the frame memory unit including memory circuitry capable of storing data representing one or more frames of the high definition video signal; an interface unit (100) including a parallel interface means for communicating with an external processing system; a parallel communications link for transferring parallel format high definition video data between the interface unit (100) and the frame memory unit (40); and a control unit (80) connected to the frame memory unit (40) and the interface unit (100), for controlling the transfer of parallel format data representing high definition video signal frames or fields into storage within the frame memory unit (40), and for controlling the transfer of stored data representing high definition video frames or fields from the memory circuitry within the frame memory unit (40) to the parallel communications link.
Claim 3
Dependent Claim
48 words
A system according to claim 1, for a high definition video signal that comprises three high definition video colour component signals, wherein the frame memory unit (40) includes means for separately storing data representing one or more frames of each of the high definition video colour component signals.
Claim 4
Dependent Claim
64 words
A system according to claim 1 or claim 2, including an input processor (10) connected to the frame memory unit (40) and the control unit (80), and including means (24, 26, 28) for converting an input high definition video signal into parallel format data representing said input high definition video signal, and for supplying said parallel format data to the frame memory unit (40).
Claim 5
Dependent Claim
112 words
A system according to claim 3, wherein the control unit (80) includes means for generating an input video selection signal and supplying the input video selection signal to the input processor (10) to switch the input processor between an analog operating state and a digital operating state, wherein the input processor (10) includes analog-to-digital conversion means (18, 20, 22) for digitising the input high definition video signal during the analog operating state, and wherein the arrangement is such that the input high definition video signal is not digitised in the analog-to-digital conversion means (18, 20, 22) before being processed in the serial-to-parallel converting means (24, 26, 28) during the digital operating state.
Claim 6
Dependent Claim
60 words
A system according to claim 3 or claim 4, for an input high definition video signal that is a digital signal having a data rate substantially equal to 74.25 MHz, which is so operative that the parallel format data is supplied to the frame memory unit (40) as a digital signal having a data rate substantially equal to 18.5625 MHz.
Claim 7
Independent Claim
73 words
A system according to any one of the preceding claims, wherein each of the control unit (80) and the interface unit (100) includes a serial interface means (82, 118) so that the control unit and the interface unit are directly connected by a serial communication link, and wherein the control unit (80) includes means (88) programmed to permit the external processor to access the frame memory unit (40) through the interface unit (100).
Claim 8
Independent Claim
82 words
A system according to any one of the preceding claims, wherein the frame memory unit (40) includes a set of memory circuits, wherein the control unit (80) includes means for supplying time-division multiplexed memory control signals to the frame memory unit (40), and wherein the frame memory unit (40) is operative to write consecutive pixel clusters of the parallel format high definition video signal data consecutively into different memory circuits in the set, in response to the time-division multiplexed memory control signals.
Claim 9
Independent Claim
40 words
A system according to any one of the preceding claims, including a post processor (60) for receiving the stored data representing high definition video fields or frames as said stored data is read out from the frame memory unit (40).
Claim 10
Dependent Claim
41 words
A system according to claim 8, wherein the control unit (80) includes means (88) programmed to read out data representing a repeating sequence of high definition video fields or frames, from the frame memory unit (40) to the post processor (40).
Claim 11
Dependent Claim
84 words
A system according to claim 8 or claim 9, wherein the post processor (60) includes a parallel-to-serial conversion means (62) for converting the parallel format data it receives from the frame memory unit (40) into a serial format signal, insertion means (66) for inserting synchronisation information into blanking intervals of the serial format signal, and means (68, 70) for simultaneously generating an analog high definition video output signal and a digital high definition video output signal from the output of the insertion means (66).
Claim 12
Independent Claim
32 words
A system according to any one of the preceding claims, wherein the frame memory unit (40) has the capacity to store data representing 32 frames of a colour high definition video signal.
Claim 13
Independent Claim
47 words
A system according to any one of the preceding claims, wherein the frame memory unit (40) includes four memory boards (42, 44, 46, 48), and wherein each of the memory boards has the capacity to store data representing 32 frames of a colour high definition video signal.
Claim 14
Independent Claim
24 words
A system according to any one of the preceding claims, wherein the control unit (80) is operative to emulate a conventional video tape recorder.
Claim 15
Independent Claim
43 words
A system according to any one of the preceding claims, wherein the frame memory unit (40) is modular, and wherein the capacity of the frame memory unit (40) may be expanded by installation of random access memory circuits in the frame memory unit.
Claim 16
Independent Claim
49 words
A system according to any one of the preceding claims, wherein the control unit (80) includes means (88) programmed to transfer stored data, representing a repeating sequence of high definition video fields or frames, from the memory circuitry within the frame memory unit (40) to the parallel communications link.
Claim 17
Dependent Claim
101 words
A high definition video signal recording system, including: a memory unit (40) for storing data representing one or more fields of a parallel format high definition video signal; an interface unit (100) connected to the memory unit (40) and including a parallel interface means (114, 116) for communicating with an external processing system; and a control unit (80) connected to the memory unit (40) and connected to the interface unit (100) by a serial communications link, for controlling the transfer of parallel data representing fields of a high definition video signal between the memory unit (40) and the interface unit (100).
Claim 18
Dependent Claim
101 words
A high definition video signal recording system, including: a memory unit (40) for storing data representing one or more fields of a parallel format high definition video signal; an interface unit (100) connected to the memory unit (40) and including a parallel interface means (114, 116) for communicating with an external processing system; and a control unit (80) connected to the memory unit (40) and connected to the interface unit (100) by a serial communications link, for controlling the transfer of parallel data representing fields of a high definition video signal between the memory unit (40) and the interface unit (100).
Claim 19
Dependent Claim
24 words
A system according to claim 16, wherein the control unit (80) includes means (88) programmed to respond to conventional video tape recorder control signals.
Claim 20
Dependent Claim
41 words
A system according to claim 16 or claim 17, including an input processor (10) connected to the control unit (80) and the memory unit (40), for supplying parallel data representing a second high definition video signal to the memory unit (40).
Claim 21
Dependent Claim
118 words
A system according to claim 18, wherein the input processor (10) includes means for receiving a colour high definition video signal having red, green, and blue component signals (12, 14, 16), means for filtering each of the component signals so that the each of the filtered component signals has a substantially flat bandwidth from 0 to 30 MHz, means (18, 20, 22) for digitising each of the filtered component signals with a first data rate, and means (24, 26, 28) for converting each of the digitised component signals into a parallel format component signal having a second data rate lower than the first data rate, the parallel format component signals together constituting said second high definition video signal.
Claim 22
Dependent Claim
71 words
A system according to claim 18, wherein the input processor (10) includes means for receiving a colour high definition video signal having red, green, and blue component signals, means (4, 6, 8) for returning at least a portion of the red, green, and blue component signals, and means (18, 20, 22, 24, 26, 28) for generating said parallel data from a non-returned portion of the red, green, and blue component signals.
Claim 23
Dependent Claim
80 words
A system according to claim 18, claim 19 or claim 20, wherein the memory unit (40) includes a plurality of memory circuits, wherein the control unit (80) includes means for supplying time-division multiplexed memory control signals to the memory unit (40), and wherein the memory unit (40) is operative to write consecutive pixel clusters of the second parallel format high definition video signal consecutively into different ones of the memory circuits in response to the time-division multiplexed memory control signals.
Claim 24
Independent Claim
35 words
A system according to any one of claims 16 to 21, wherein the memory unit (40) is modular, and wherein the capacity of the memory unit is expandable by installation of additional memory boards therein.
Claim 25
Independent Claim
76 words
A system according to any one of claims 16 to 22, wherein each of the control unit (80) and the interface unit (100) includes a serial interface means (82, 118), so that the control unit and the interface unit are directly connected by a serial communication link, and wherein the control unit (80) includes means (88) programmed to permit an external processor to access the frame memory unit (40) through the parallel interface means (114, 116).
Claim 26
Dependent Claim
102 words
A system according to claim 23, wherein the control unit (80) includes means for generating and forwarding address and control signals to the memory unit (40) in response to commands received from the external processor through the serial communication link from the parallel interface means (114, 116) of the interface unit (100), and wherein the interface unit (100) includes means (104) for receiving data representing a colour high definition video signal and converting said data into parallel data, and means (102) for transferring the parallel data to the memory unit (40) for recording therein in response to the address and control signals.
Claim 27
Independent Claim
82 words
A system according to any one of claims 16 to 23, wherein the interface unit (100) includes a first-in-first-out circuit (102) and a central processing unit (CPU) bus (124), wherein the parallel interface means (114, 116) is connected to the CPU bus (124), and wherein the first-in-first-out circuit (102) is connected between the memory unit (40) and the CPU bus (124), so that all data transfers between the interface unit (100) and the memory unit (40) flow through the first-in-first-out circuit (102).
References Cited (Backward Citations)
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