CPU-bus controller

Claim 2

Apparatus for controlling an input/output bus interface between a microprocessor and accessible devices on the input/output bus, said apparatus comprising: state machine means coupled to an input/output bus and responsive to command signals from a microprocessor and to control signals from accessible devices on said input/output bus for generating input/output bus control signals coupled to said input/output bus, said microprocessor and said accessible devices for initiating and controlling access operations on said input/output bus; and detection means coupled to said microprocessor, said input/output bus and said state machine and responsive to said command signals and said input/output bus control signals for detection of a last access cycle of a current access operation and generating a last cycle signal indicative of detection of said last access cycle.

Claim 3

Apparatus as in Claim 1 wherein said state machine means is responsive to said last cycle signal for generating a ready signal at the completion of an access operation indicating that said apparatus is ready to receive a next requested operation.

Claim 4

Apparatus as in Claim 1 further comprising status interpreter means coupled to said microprocessor and said state machine means and responsive to said command signals and to information signals from said input/output bus for determining the type of operation requested and for generating state machine command signals coupled to said state machine means, said state machine means responsive to said state machine command signals to initiate the requested operation.

Claim 5

Apparatus as in Claim 3 further including enable detect means coupled to said microprocessor and said input/output bus and responsive to said command signals for generating input/output bus data enable signals.

Claim 6

Apparatus as in Claim 4 further comprising buffer control means coupled to said state machine, said input/output bus, said detection means and said enable detect means for generating enable and direction control signals coupled to data path and address buffer means.

Claim 7

Apparatus as in Claim 1 further including clock generating means responsive to a plurality of master clock input signals for generating a plurality of clock signals derived from said plurality of master clock input signals for use by components of said apparatus and externals system components.

Claim 8

Apparatus as in Claim 1 further comprising reset control means responsive to reset control signals for generating a system reset signal.

Claim 9

Apparatus as in Claim 3 wherein said state machine means is responsive to said state machine command signals for generating a system shutdown signal and a halt signal.

Claim 10

An input/output bus controller for controlling access operations between multiple processors and accessible devices on an input/output bus, said input/output bus controller comprising: state machine means coupled to an input/output bus and to at least one processor on said input/output bus responsive to command signals from said processor and to control signals from accessible devices on said input/output bus for initiating and controlling requested access operations on said input/output bus; processor interface means coupled to said processor and said input/output bus responsive to said command signals and said control signals for determining the type of access operation requested by said processor and generating stimulus signals coupled to said state machine means to initiate the requested access; and buffer control means coupled to said state machine means, said processor interface means, said input/output bus and to input/output bus address and data buffer means, said buffer control means for generating enable and data flow control signals for controlling said address and data buffers.

Claim 11

An input/output bus controller for controlling access operations between multiple processors and accessible devices on an input/output bus, said input/output bus controller comprising: state machine means coupled to an input/output bus and to at least one processor on said input/output bus responsive to command signals from said processor and to control signals from accessible devices on said input/output bus for initiating and controlling requested access operations on said input/output bus; processor interface means coupled to said processor and said input/output bus responsive to said command signals and said control signals for determining the type of access operation requested by said processor and generating stimulus signals coupled to said state machine means to initiate the requested access; and buffer control means coupled to said state machine means, said processor interface means, said input/output bus and to input/output bus address and data buffer means, said buffer control means for generating enable and data flow control signals for controlling said address and data buffers.

Claim 12

An input/output bus controller as in Claim 9 wherein said processor interface means includes detection means responsive to said command signals and said control signals for detection of a last access cycle of a current access operation and generating a last cycle signal indicative of detection of said last access cycle.

Claim 13

An input/output bus controller as in Claim 10 wherein said multiple processors and said accessible devices may have different data widths, said bus controller controlling requested access operations between said processors and accessible devices having different data widths.

Claim 14

An input/output bus controller as in Claim 11 wherein said processor interface means further includes enable detection means responsive to said command signals and said control signals for determining the data width of said processor and for generating enable signals indicative of data bytes required to satisfy a current processor access request.

Claim 15

An input/output bus controller as in Claim 12 wherein said processor interface includes status means responsive to said command signals and said control signals for determining the type of access operation requested and generating said stimulus signals coupled to said state machine means.

Claim 16

An input/output bus controller as in Claim 9 further clock comprising clock generating means responsive to a plurality of clock signals derived from said plurality of master clock input signals for use by components of said bus controller and system components external to said bus controller.

Claim 17

An input/output bus controller as in Claim 9 further comprising reset control means responsive to reset control system for generating a system reset signal.

Claim 18

An input/output bus controller as in Claim 13 wherein said bus controller is implemented in a VLSI chip.

Claim 19

An input/output bus controller as in Claim 13 wherein said state machine means generates a halt signal or a shutdown signal in response to corresponding stimulus signals generated by status means.

Claim 20

An input/output bus controller as in Claim 9 wherein said bus controller is a synchronous controller.

Claim 21

An input/output bus controller as in Claim 18 wherein said wherein said input/output bus is an asynchronous bus.

Claim 24

The method of Claim 20 wherein said step of determining the last cycle includes the steps of: determining the data bytes requested in a processor access request; determining the data width of the requesting processor; and determining the data width of the accessed controllable device.

Claim 25

The method of Claim 21 wherein said step of generating a ready signal includes the steps of: comparing the highest requested data byte address with the current access cycle data byte address; and generating said ready signal when said highest requested data byte address matches a current access cycle byte address.