Bitline segmentation in logic memory arrays

Claim 2

A non-volatile memory array comprising: a plurality rows of modules, each said module including a plurality of rows of memory cells and a plurality of columns of memory cells, wherein each memory cell has a control electrode and a current path between first and second electrodes; a plurality of row lines, each said row line connected to said control electrodes of each memory cell in each said row of memory cells; a plurality of ground-column lines and of segmented output-column lines, each of said first electrodes of said memory cells connected to a said ground-column line, each of said second electrodes of said memory cells connected to a said segmented output-column line, each said segmented output-column line connected to an input/output circuit line through a first logic switch; a row decode means for selecting and accessing said row lines; a column decode means for selecting and activating said segmented output-column lines; wherein each of said wordlines of a said module is electrically connected to a wordline of each of the others of said modules; and wherein outputs of said column decode means are electrically connected to each of the gates of said first logic switch.

Claim 3

The memory array of Claim 1, wherein said ground-­column lines of said memory array are segmented, wherein each said ground-column line is electrically connected at one end to a voltage supply source and is electrically connected at the other end through a second logic switch to a source of reference potential, and wherein outputs of said column decode means are electrically connected to each of the gates of said second logic switch.

Claim 4

The memory array of Claim 1, wherein each of said first logic switches of a said module is electrically connected to said input/output circuit through a third logic switch, and wherein third logic switch is electrically connected to an output of said column decode means.

Claim 5

The memory array of Claim 1, wherein each said ground-­column line of said memory array is segmented, wherein each of said second electrodes of memory cells in said segmented column of cells in a module is connected to a said segmented ground-­column line, wherein said ground-column line is electrically connected at one end to a voltage supply source and is electrically connected at the other end through a second logic switch to a source of reference potential, wherein outputs of said column decode means are electrically connected to each of the gates of said second logic switches, wherein each of said second logic switches of a said module is electrically connected to said input/output circuit through a fourth logic switch, and wherein said fourth logic switch is electrically connected to an output of said column decode means.

Claim 6

A non-volatile memory array comprising: a plurality rows of modules, each said module including a plurality of rows of memory cells and a plurality of columns of memory cells, wherein each memory cell has a control gate and a current path between a source and a drain; a plurality of row lines, each said row line connected to said control gate of each memory cell in each said row of memory cells; a plurality of segmented column lines, each source said memory cells connected to a said segmented column line, each drain of said memory cells connected to another said segmented column line, each said segmented column line connected one of either a source of electrical potential or, through a first pass-­gate transistor, to an input/output circuit; a row decode circuit for selecting and accessing said row lines; a column decode circuit for selecting and activating said segmented column lines; wherein each of said wordlines of a said module is electrically connected to a wordline of each of the others of said modules; and wherein outputs of said column decode circuit are electrically connected to each of the gates of said first pass-­gate transistors.

Claim 7

A non-volatile memory array comprising: a plurality rows of modules, each said module including a plurality of rows of memory cells and a plurality of columns of memory cells, wherein each memory cell has a control gate and a current path between a source and a drain; a plurality of row lines, each said row line connected to said control gate of each memory cell in each said row of memory cells; a plurality of segmented column lines, each source said memory cells connected to a said segmented column line, each drain of said memory cells connected to another said segmented column line, each said segmented column line connected one of either a source of electrical potential or, through a first pass-­gate transistor, to an input/output circuit; a row decode circuit for selecting and accessing said row lines; a column decode circuit for selecting and activating said segmented column lines; wherein each of said wordlines of a said module is electrically connected to a wordline of each of the others of said modules; and wherein outputs of said column decode circuit are electrically connected to each of the gates of said first pass-­gate transistors.

Claim 8

The memory array of Claim 5, wherein each alternating said segmented-column line is electrically connected at one end to a voltage supply source and is electrically connected at the other end through a second pass-gate transistor to a source of reference potential, and wherein outputs of said column decode circuit are electrically connected to each of the gates of said second pass-gate transistors.

Claim 9

The memory array of Claim 5, wherein each of said first pass-gate transistors of a said module is electrically connected to said input/output circuit through a third pass-gate transistor, and wherein the gate of said third pass-gate transistor is electrically connected to an output of said column decode circuit.

Claim 10

The memory array of Claim 5, wherein each alternating said segmented column line of said memory array is electrically connected at one end to a voltage supply source and is electrically connected at the other end through a second pass-­gate transistor to a source of reference potential, wherein outputs of said column decode circuit are electrically connected to each of the gates of said second pass-gate transistors, wherein each of said second pass-gate transistors of a said module is electrically connected to said input/output circuit through a fourth pass-gate transistor, and wherein the gate of said fourth pass-gate transistor is electrically connected to an output of said column decode circuit.

Claim 11

A non-volatile memory array comprising: a plurality rows and columns of modules, each said module including a plurality of rows of memory cells and a plurality of columns of memory cells, wherein each memory cell has a control electrode and a current path between first and second electrodes; a plurality of row lines, each said row line connected to said control electrodes of each memory cell in each said row of memory cells; a plurality of ground-column lines and of segmented output-column lines, each of said first electrodes of said memory cells connected to a said ground-column line, each of said second electrodes of said memory cells connected to a said output-column line, each said ground-column line connected to at least one source of voltage potential, each said output-column line connected through a first logic switch and through a third logic switch, to an input/output circuit; a row decode circuit for selecting and accessing said row lines; a column decode circuit for selecting and activating said segmented output-column lines; wherein each of said wordlines of a said module is electrically connected to a wordline of each of the others of said modules; wherein each of said output-column lines of a said module is electrically connected to an output-column line of each of the others of said modules; and wherein outputs of said column decode circuit are electrically connected to each of the gates of said first logic switches and said third logic switches.

Claim 12

A non-volatile memory array comprising: a plurality rows and columns of modules, each said module including a plurality of rows of memory cells and a plurality of columns of memory cells, wherein each memory cell has a control electrode and a current path between first and second electrodes; a plurality of row lines, each said row line connected to said control electrodes of each memory cell in each said row of memory cells; a plurality of ground-column lines and of segmented output-column lines, each of said first electrodes of said memory cells connected to a said ground-column line, each of said second electrodes of said memory cells connected to a said output-column line, each said ground-column line connected to at least one source of voltage potential, each said output-column line connected through a first logic switch and through a third logic switch, to an input/output circuit; a row decode circuit for selecting and accessing said row lines; a column decode circuit for selecting and activating said segmented output-column lines; wherein each of said wordlines of a said module is electrically connected to a wordline of each of the others of said modules; wherein each of said output-column lines of a said module is electrically connected to an output-column line of each of the others of said modules; and wherein outputs of said column decode circuit are electrically connected to each of the gates of said first logic switches and said third logic switches.

Claim 13

The memory array of Claim 9, wherein said ground-­column lines of said memory array are segmented, wherein each said ground-column line is electrically connected at one end to a voltage supply source and is electrically connected at the other end through a second logic switch to a source of reference potential, and wherein outputs of said column decode circuit are electrically connected to each of the gates of said second logic switches.

Claim 14

The memory array of Claim 9, wherein each said ground-­column line of said memory array is segmented, wherein each of said second electrodes of memory cells in said segmented column of cells in a module is connected to a said segmented ground-­column line, wherein said ground-column line is electrically connected at one end to a voltage supply source and is electrically connected at the other end through a second logic switch to a source of reference potential, wherein outputs of said column decode circuit are electrically connected to each of said second logic switch, wherein each of said second logic switches of a said module is electrically connected to said input/output circuit through a fourth logic switch, and wherein said fourth logic switch is electrically connected to an output of said column decode circuit.