EP0421696A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Staggered access memory
Assignee: Motorola Solutions Inc
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Filing: 1990-09-28
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Granted: —
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Expires: 2010-09-28
Abstract
Abstract A data processing system in which a plurality of processors, intelligent controllers, or other memory access devices (1, 2, 42, 43 or 50) operate either synchronously or asynchronously with a memory interface device (3), which in turn provides access to one or more memory units (8 and 9) on a time-division basis. This is accomplished by providing each memory unit (8 and 9) a series of time-divisioned access opportunities and controlling the phase relationship between these time-divisioned access opportunities. Accordingly, two or more access devices (1 2, 42, 43 or 50) can address an equal number of memory unit(s) (8 and 9) simultaneously.
Inventors
- 👤 John M. Kaczmarczyk
- 👤 Dale R. Buchholz
- 👤 Jeffrey A. Slawecki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 18:16
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1663; G06F13/1657; G06F13/1668; G06F13/1689
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
89 words
A data processing system having a plurality of memory units (8 and 9) having access times, a memory interface device (3) connected to the plurality of memory units (8 and 9) for addressing the memories on a time-division basis, and a plurality of memory access devices (1 and 2) exhibiting memory access characteristics, the improvement characterized by: memory interface device (3) being connected to the plurality of memory access devices (1 and 2) for simultaneously providing data to the plurality of memory access devices (1 and 2) upon demand.
Claim 2
Dependent Claim
89 words
A data processing system having a plurality of memory units (8 and 9) having access times, a memory interface device (3) connected to the plurality of memory units (8 and 9) for addressing the memories on a time-division basis, and a plurality of memory access devices (1 and 2) exhibiting memory access characteristics, the improvement characterized by: memory interface device (3) being connected to the plurality of memory access devices (1 and 2) for simultaneously providing data to the plurality of memory access devices (1 and 2) upon demand.
Claim 3
Dependent Claim
79 words
The data processing system of claim 1 further comprising data bus means (6 and 7) connected to the memory interface device (3) and the memory units (8 and 9) for passing information between the plurality of memory units (8 and 9) and the memory interface device (3); and further wherein said memory interface device (3) includes logic means (14 and 15) for creating memory select and enable signals for simultaneously enabling the plurality of memory units (8 and 9).
Claim 4
Dependent Claim
86 words
The data processing system of claim 1 further comprising data bus means (4 and 5) connected to the memory interface device (3) and said plurality of memory access devices (1 and 2) for passing information between the memory interface device (3) and the plurality of memory access devices (1 and 2); and further wherein said plurality of memory access devices (1 and 2) include means for generating memory access device information to initiate the addressing of one of said plurality of memory units (8 or 9).
Claim 5
Dependent Claim
147 words
The data processing system according to claim 3, wherein the memory interface device (3) further comprises: a) receiving means (10 and 11) for accepting and storing memory access device information from a memory access device (1 or 2) attempting to address at least one of the plurality of memory units (8 or 9); b) memory addressing means (20) responsive to the receiving means (10 and 11) for selecting a specific memory among the plurality of memory units (8 and 9); and c) controller means (14 and 15) operably coupled to the memory addressing (20) means and the receiving means (10 and 11) for controlling communication between a memory access device (1 and 2) and the plurality of memory units (8 or 9), such that each memory is accessible by one of the memory access devices (1 or 2) during the memory access time associated with that memory.
Claim 6
Dependent Claim
39 words
The data processing system of claim 1, wherein said memory access characteristics comprise at least one of: a) synchronous operation with the memory interface device; b) asynchronous operation with the memory interface device; and c) an operating time cycle.
Claim 7
Dependent Claim
27 words
The data processing system of claim 1, wherein said memory access times are one of: a) substantially identical to one another; and b) different from one another.
Claim 8
Dependent Claim
37 words
The data processing system of claim 1, wherein said plurality of memory access devices (1 and 2) have operating time cycles which are one of: a) substantially identical to one another; and b) different from one another.
Claim 9
Dependent Claim
152 words
In a system comprising a plurality of memory units (8 and 9) having access times, and a plurality of memory access devices (1 and 2) exhibiting memory access characteristics, a method of simultaneously interfacing the memory units (8 and 9) with the memory access devices (1 and 2) characterized by: a) receiving memory access device access requests from memory access devices (1 and 2) attempting to address one of said plurality of memory units (8 or 9); b) providing a first series of synchronizing memory access opportunities for a first memory unit (8), while simultaneously; c) providing a second series of synchronizing memory access opportunities for a second memory unit (9); d) synchronizing some of the access requests with the memory access opportunities associated with the first memory unit; and e) synchronizing at least some of the remaining access requests with the memory access opportunities associated with the second memory unit (9).
Claim 10
Dependent Claim
152 words
In a system comprising a plurality of memory units (8 and 9) having access times, and a plurality of memory access devices (1 and 2) exhibiting memory access characteristics, a method of simultaneously interfacing the memory units (8 and 9) with the memory access devices (1 and 2) characterized by: a) receiving memory access device access requests from memory access devices (1 and 2) attempting to address one of said plurality of memory units (8 or 9); b) providing a first series of synchronizing memory access opportunities for a first memory unit (8), while simultaneously; c) providing a second series of synchronizing memory access opportunities for a second memory unit (9); d) synchronizing some of the access requests with the memory access opportunities associated with the first memory unit; and e) synchronizing at least some of the remaining access requests with the memory access opportunities associated with the second memory unit (9).
Claim 11
Dependent Claim
42 words
The method of claim 8, wherein step (a) of receiving memory access device access requests, further comprises the steps of: A.1) decoding said memory access device access request;and A.2) addressing a memory unit among said plurality of memory units (8 and 9).
Claim 12
Dependent Claim
24 words
The method of claim 8 wherein said first and second series of synchronizing memory access opportunities have a predetermined in-phase relationship to each other.
Claim 13
Dependent Claim
52 words
The method of claim 8 wherein said steps (b) and (c) of providing a first and a second series of synchronizing memory access opportunities further comprises the steps of: a) obtaining a clock signal (23); b) routing said clock signal (23) to a counter (21); and c) dividing the counter (21) output.
Claim 14
Dependent Claim
32 words
The method of claim 8 wherein the synchronizing step further comprises the steps of: 1) recognizing an incomplete access opportunity; and 2) synchronizing said access request upon a next valid access opportunity.
Claim 15
Dependent Claim
163 words
A memory interface device (3) for use in interfacing: at least a first memory (8) having an access time with, at least a first memory access device (1) having a memory access characteristic, and a second memory access device (2) having a memory access characteristic, the memory interface device (3) comprising: a) receiving means (10 and 11) for accepting and storing memory access device information from one of a plurality of memory access devices (1 or 2) attempting to address memory; b) memory addressing means (20) responsive to the receiving means (10 and 11) for addressing memory (8) wherein the improvement is characterized by: c) controller means (14 and 15) operably coupled to the memory addressing means (20) and the receiving means (10 and 11) for controlling coupling between a memory access device (1 or 2) and memory, such that memory is accessible by one of the memory access devices (1 or 2) during a memory access opportunity provided that memory access device.
Claim 16
Dependent Claim
163 words
A memory interface device (3) for use in interfacing: at least a first memory (8) having an access time with, at least a first memory access device (1) having a memory access characteristic, and a second memory access device (2) having a memory access characteristic, the memory interface device (3) comprising: a) receiving means (10 and 11) for accepting and storing memory access device information from one of a plurality of memory access devices (1 or 2) attempting to address memory; b) memory addressing means (20) responsive to the receiving means (10 and 11) for addressing memory (8) wherein the improvement is characterized by: c) controller means (14 and 15) operably coupled to the memory addressing means (20) and the receiving means (10 and 11) for controlling coupling between a memory access device (1 or 2) and memory, such that memory is accessible by one of the memory access devices (1 or 2) during a memory access opportunity provided that memory access device.
Claim 17
Dependent Claim
27 words
The memory interface device (3) of claim 13 further comprising counter means (21) for generating memory access opportunities (24 and 25) supportive of memory interface device synchronization.
Claim 18
Dependent Claim
49 words
The memory interface device (3) of claim 13 wherein said first and second memory access devices (1 and 2) have a memory access characteristic comprising one of: a) synchronous operation with the memory interface device; b) asynchronous operation with the memory interface device; and c) an operating time cycle.
References Cited (Backward Citations)
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