EP0421627A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Memory device
Assignee: Advanced Micro Devices Inc
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Filing: 1990-09-17
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Granted: —
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Expires: 2010-09-17
Abstract
Abstract A high speed dual-port burst access memory (BAM) is disclosed that is capable of operating in both a burst access mode and random access mode simultaneously. The architecture of the high speed BAM permits random or burst access read or write operations on one port while simultaneously supporting sequential reading or writing in a burst or random mode of operation on a second port. Burst access can also be stopped and restarted for any number of clock cycles independently at each port. The BAM can also be configured as a high speed FIFO.
Inventors
- 👤 David C. Wyland
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-10 02:17
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/16; G06F5/10; G06F7/00; G06F7/60; G06F7/62
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
144 words
An apparatus comprising: first and second address counters; addressing means for loading address values in said first and second address counters; first and second memory arrays; address multiplexing means for selectively applying the address values loaded in said first and second address counters to said first and second memory arrays; first and second reversible FIFOs; data multiplexing means for selectively connecting said first and second reversible FIFOs to said first and second memory arrays; control means for controlling the operation of said first and second reversible FIFOs and said data multiplexing means to supply data words from said first and second reversible FIFOs to said first and second memory arrays in a write access mode of operation, and to selectively supply data words stored in said first and second memory arrays to said first and second FIFOs in a read access mode of operation.
Claim 2
Independent Claim
144 words
An apparatus comprising: first and second address counters; addressing means for loading address values in said first and second address counters; first and second memory arrays; address multiplexing means for selectively applying the address values loaded in said first and second address counters to said first and second memory arrays; first and second reversible FIFOs; data multiplexing means for selectively connecting said first and second reversible FIFOs to said first and second memory arrays; control means for controlling the operation of said first and second reversible FIFOs and said data multiplexing means to supply data words from said first and second reversible FIFOs to said first and second memory arrays in a write access mode of operation, and to selectively supply data words stored in said first and second memory arrays to said first and second FIFOs in a read access mode of operation.
Claim 3
Dependent Claim
25 words
An apparatus as claimed in claim 1, further comprising means for sequentially incrementing said first and second address counters in a burst mode of operation.
Claim 4
Dependent Claim
84 words
An apparatus as claimed in claim 1, further comprising a flag counter controlled by said control means, wherein said flag counter is incremented by said control means when a write operation is performed and a data word is stored in at least one of said first and second memory arrays, and said flag counter is decremented by said control means when a read operation is performed and a data word is read in from at least one of said first and second memory arrays.
References Cited (Backward Citations)
No citation records indexed.
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