EP0421446A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device wherein n-channel MOSFET, p-channel MOSFET and nonvolatile memory cell are formed in one chip
Assignee: Toshiba Corp
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Filing: 1990-10-05
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Granted: —
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Expires: 2010-10-05
Abstract
Abstract An n-channel MOSFET (102), a p-channel MOSFET (104) and a nonvolatile memory cell (100) are provided for the same semiconductor substrate (1). The nonvolatile memory cell (100) is formed on the semiconductor substrate (1), the n-channel MOSFET (102) is formed in a p-type well region (11) of the semiconductor substrate (1), and the p-channel MOSFET (104) is formed in an n-type well region (12) of the semiconductor substrate (1).
Inventors
- 👤 Teruo C/O Intellectual Property Div. Uemura
- 👤 Naoki C/O Intellectual Property Div. Hanada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 06:16
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
402 words
A semiconductor device characterized by comprising: a semiconductor substrate (1) which has a major surface and is of a first conductivity type; first and second semiconductor regions (31, 32) which are formed in the major surface of the substrate (1) while being isolated from each other and which are of a second conductivity type; carrier accumulation means (5) for accumulating carriers, said carrier accumulation means being formed above that surface portion of the substrate (1) which is located between the first and second semiconductor regions (31, 32); first insulation means (4), located between the carrier accumulation means (5) and the substrate (1), for electrically insulating the carrier accumulation means (5) and the substrate (1) from each other; a first conductive layer (10) formed above the carrier accumulation means (5); second insulation means (9), located between the first conductive layer (10) and the carrier accumulation means (5), for electrically insulating the first conductive layer (10) and the carrier accumulation means (5) from each other; a first well region (11) which is formed in the major surface of the substrate (1) and is of the first conductivity type; third and fourth semiconductor regions (131, 132) which are formed in a surface region of the first well region (11) while being isolated from each other and which are of the second conductivity type; a second conductive layer (15) formed above that surface portion of the first well region (11) which is located between the third and fourth semiconductor regions (13₁, 13₂); third insulation means (14), located between the second conductive layer (15) and the first well region (11), for electrically insulating the second conductive layer (15) and the first well region (11) from each other; a second well region (12) which is formed in the major surface of the substrate (1) and is of the second conductivity type; fifth and sixth semiconductor regions (161, 162) which are formed in a surface region of the second well region (12) while being isolated from each other and which are of the first conductivity type; a third conductive layer (18) formed above that surface portion of the second well region (12) which is located between the fifth and sixth semiconductor regions (16₁, 16₂); and fourth insulation means (17), located between the third conductive layer (18) and the second well region (12), for electrically insulating the third conductive layer (18) and the second well region (12) from each other.
Claim 2
Dependent Claim
402 words
A semiconductor device characterized by comprising: a semiconductor substrate (1) which has a major surface and is of a first conductivity type; first and second semiconductor regions (31, 32) which are formed in the major surface of the substrate (1) while being isolated from each other and which are of a second conductivity type; carrier accumulation means (5) for accumulating carriers, said carrier accumulation means being formed above that surface portion of the substrate (1) which is located between the first and second semiconductor regions (31, 32); first insulation means (4), located between the carrier accumulation means (5) and the substrate (1), for electrically insulating the carrier accumulation means (5) and the substrate (1) from each other; a first conductive layer (10) formed above the carrier accumulation means (5); second insulation means (9), located between the first conductive layer (10) and the carrier accumulation means (5), for electrically insulating the first conductive layer (10) and the carrier accumulation means (5) from each other; a first well region (11) which is formed in the major surface of the substrate (1) and is of the first conductivity type; third and fourth semiconductor regions (131, 132) which are formed in a surface region of the first well region (11) while being isolated from each other and which are of the second conductivity type; a second conductive layer (15) formed above that surface portion of the first well region (11) which is located between the third and fourth semiconductor regions (13₁, 13₂); third insulation means (14), located between the second conductive layer (15) and the first well region (11), for electrically insulating the second conductive layer (15) and the first well region (11) from each other; a second well region (12) which is formed in the major surface of the substrate (1) and is of the second conductivity type; fifth and sixth semiconductor regions (161, 162) which are formed in a surface region of the second well region (12) while being isolated from each other and which are of the first conductivity type; a third conductive layer (18) formed above that surface portion of the second well region (12) which is located between the fifth and sixth semiconductor regions (16₁, 16₂); and fourth insulation means (17), located between the third conductive layer (18) and the second well region (12), for electrically insulating the third conductive layer (18) and the second well region (12) from each other.
Claim 3
Dependent Claim
26 words
A semiconductor device according to claim 1, characterized in that said first, second, third and fourth insulation means (4, 9, 14, 17) include insulation films, respectively.
Claim 4
Dependent Claim
20 words
A semiconductor device according to claim 1, characterized in that said carrier accumulation means (5) include a fourth conductive layer.
Claim 5
Dependent Claim
45 words
A semiconductor device according to claim 1, characterized in that said substrate (1) has an impurity concentration of ρ1, and said first well region (11) has an impurity concentration of ρ2, said impurity concentrations ρ1 and ρ2 having a relationship expressed by: ρ1 < ρ2.
Claim 6
Dependent Claim
116 words
A semiconductor device characterized by comprising: a semiconductor substrate (1) which has a major surface and is of a first conductivity type; a first active element (100) formed in the major surface of the semiconductor substrate (1); a first well region (11) which is formed in the major surface of the substrate (1) and is of the first conductivity type; a second active element (102) formed in a surface region of the first well region (11); a second well region (12) which is formed in the major surface of the substrate (1) and is of a second conductive type; and a third active element (104) formed in a surface region of the second well region (12).
Claim 7
Dependent Claim
116 words
A semiconductor device characterized by comprising: a semiconductor substrate (1) which has a major surface and is of a first conductivity type; a first active element (100) formed in the major surface of the semiconductor substrate (1); a first well region (11) which is formed in the major surface of the substrate (1) and is of the first conductivity type; a second active element (102) formed in a surface region of the first well region (11); a second well region (12) which is formed in the major surface of the substrate (1) and is of a second conductive type; and a third active element (104) formed in a surface region of the second well region (12).
Claim 8
Dependent Claim
20 words
A semiconductor device according to claim 5, characterized in that said first active element (100) is a nonvolatile memory cell.
Claim 9
Dependent Claim
22 words
A semiconductor device according to claim 6, characterized in that said nonvolatile memory cell includes carrier accumulation means (5) for accumulating carriers.
Claim 10
Dependent Claim
19 words
A semiconductor device according to claim 7, characterized in that said carrier accumulation means (5) includes a conductive layer.
Claim 11
Dependent Claim
21 words
A semiconductor device according to claim 5, characterized in that said second and third active elements (102, 104) are MOSFETs, respectively.
Claim 12
Dependent Claim
45 words
A semiconductor device according to claim 5, characterized in that said substrate (11) has an impurity concentration of pl, and said first well region (11) has an impurity concentration of p2, said impurity concentrations ρ1 and ρ2 having a relationship expressed by: ρ1 < ρ2.
References Cited (Backward Citations)
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