A computer system with a sleep function

Claim 2

A computer system with a sleep function, including the processor means (10) to configure the central processing unit of the system and execute various data processings and the I/O means (11, 15) to execute input/output of data, comprising: the clock generator means (20) for generating the clock pulse necessary for operation of the said processor means (10); characterized by further comprising: the register means (34) for storing the data to designate that the said processor means (10) is idle; and, the sleep control means (17) for setting the sleep mode according to the data stored in the said register means (34), controlling feed of the said clock pulse sent from the said clock generator means (20), and stopping the operation of the said processor means (10) or decreasing the operation speed of it.

Claim 3

A system according to claim 1, comprising a logic circuit (27, 30) having a flip-flop circuit (34) which is reset when the said register means (34) latches the logic level data under the condition in which the said I/O means (11, 15) is not accessed within a certain period as the data to designate the said idle state and the said I/O means (11, 15) is accessed.

Claim 4

A system according to claim 1, characterized in that said sleep control means (17) has the register means (34) for sleep mode to latch the data to designate the sleep mode when the said processor means (10) reads the data stored in the said register means (34) and the logic circuit (21) to stop feeding the said clock pulse from the said clock generator means (20) to the said processor means (10).

Claim 5

A system according to claim 1, further comprising: the transfer means (37, 41) for transferring the data stored in the said register means (34) to the said processor means (10) according to the read operation of the said processor means (10).

Claim 6

A system according to claim 1, further comprising: the indicator (50) to designate that the said sleep control means (17) is in the sleep mode when the sleep mode is set.

Claim 7

A system according to claim 1, characterized in that said sleep control means (17) has the clock frequency dividing means (60) to output the low-­frequency clock pulse obtained by dividing the said clock pulse sent from the said clock generator means (20) and the control is executed to feed the said low-­frequency clock pulse output from the said clock frequency dividing means to the said processor means (60) to the said processor means (10) when the sleep mode is set.

Claim 8

A system according to claim 2, further comprising: the transfer means (37, 41) for transferring the data latched by the said flip-flop circuit (34) of the said register means (34) to the said processor means (10) according to the read operation of the said processor means (10).

Claim 9

A system according to claim 3, further comprising: the said sleep control means (17) which has the clearing means (28, 39) to clear the data latched by the said sleep-mode register means (35) when the interrupt signal output by the said I/O means (11, 15) is input.

Claim 10

A computer system with a sleep function, including the processor means (10) to configure the central processing unit of the system and execute various data processings, the I/O means (11, 15) to execute input and output of data, and the basic I/O system to control data input/output operation by the said I/O means, comprising: the clock generator means (20) for generating the clock pulse necessary for the operation of the said processor means (10) and feed the pulse to the said processor means (10); characterized by further comprising: the register means (34) for storing the data to designate the idle state of the said processor means (10); the transfer means (37, 41) for transferring the data stored in the said register means (34) to the said processor means (10) according to the read operation of the said processor means (10) so that the said basic I/O system can detect the idle state of the said processor means (10) according to the data stored in the said register means (34); and, the sleep control means (17) for stopping the operation of the said processor means (10) or decrease the operation speed by setting the sleep mode and controlling feed of the said clock pulse output by the said clock generator means (20) when the said basic I/O system detects the idle state of the said processor means (10).

Claim 11

A computer system with a sleep function, including the processor means (10) to configure the central processing unit of the system and execute various data processings, the I/O means (11, 15) to execute input and output of data, and the basic I/O system to control data input/output operation by the said I/O means, comprising: the clock generator means (20) for generating the clock pulse necessary for the operation of the said processor means (10) and feed the pulse to the said processor means (10); characterized by further comprising: the register means (34) for storing the data to designate the idle state of the said processor means (10); the transfer means (37, 41) for transferring the data stored in the said register means (34) to the said processor means (10) according to the read operation of the said processor means (10) so that the said basic I/O system can detect the idle state of the said processor means (10) according to the data stored in the said register means (34); and, the sleep control means (17) for stopping the operation of the said processor means (10) or decrease the operation speed by setting the sleep mode and controlling feed of the said clock pulse output by the said clock generator means (20) when the said basic I/O system detects the idle state of the said processor means (10).

Claim 12

A system according to claim 9, characterized in that said register means (34) comprises the logic circuit (27, 30) having the flip-flop circuit (34) which latches the logic level data under the condition in which the said I/O means (11, 15) is not accessed within a certain period as the data to designate the said idle state and which is reset when the said I/O means (11, 15) is accessed.

Claim 13

A system according to claim 9, characterized in that said sleep control means (17) has the register means (34) for sleep mode to latch the data to designate the sleep mode when the said processor means (10) reads the data stored in the said register means (34) and the logic circuit (21) to stop feeding the said clock pulse from the said clock generator means (20) to the said processor means.

Claim 14

A system according to claim 9, further comprising: the indicator (50) to designate that the said sleep control means (17) is in the sleep mode when the sleep mode is set.

Claim 15

A system according to claim 9, characterized in that said sleep control means (17) has the clock frequency dividing means (60) to output the low-­frequency clock pulse obtained by dividing the said clock pulse sent from the said clock generator means (20) and the control is executed to feed the said low-­frequency clock pulse output from the said clock frequency dividing means (60) when the sleep mode is set.

Claim 16

A system according to claim 10, further comprising: the transfer means (37, 41) to transfer the data latched by the said flip-flop circuit (34) of the said register means (34) to the said processor means (10) according to the read operation of the said processor means (10).

Claim 17

A system according to claim 11, further comprising: the said sleep control means (17) which has the clearing means (28, 39) to clear the data latched by the said sleep-mode register (35) means when the interrupt signal output by the said I/O means (11, 15) is input.