Semiconductor memory device having capacitor through which data read/write is carried out

Claim 2

A semiconductor memory device comprising: at least one memory cell (MC) having first and second nodes (A, B); and a pair of bit lines (BL, BL ) coupled to said memory cell, characterized in that there are provided: a first power line (V DD ) which is coupled to said memory cell (MC) for supplying a first power source voltage (V DD ); and a second power line (V SS ) which is coupled to said memory cell for supplying a second power source voltage (V SS ); that said memory cell (MC) includes a first resistor (R1) connected between said first power line and said first node (A), a first transistor (Q1) connected between said first node and said second power line, a second resistor (R2) connected between said first power line and said second node (B), a second transistor (Q2) connected between said second node and said second power line, a first capacitor (C1) connected between one (BL) of said bit lines and said first node, and a second capacitor (C2) connected between the other ( BL ) of said bit lines and said second node; that said first transistor (Q1) has a gate which is connected to said second node; that said second transistor (Q2) has a gate which is connected to said first node; and that one of said first and second power lines (V DD , V SS ) is used in common as a word line (MWL).

Claim 3

The semiconductor memory device as claimed in claim 1, characterized in that said first power line (V DD ) supplies the first power source voltage (V DD ) which is a positive voltage and said second power line (V SS ) supplies the second power source voltage (V SS ) which is a negative voltage.

Claim 4

The semiconductor memory device as claimed in claim 1 or 2, characterized in that there is further provided a sense amplifier (SA) which is connected to said bit lines (BL, BL ), said sense amplifier amplifying a potential difference across said bit lines.

Claim 5

The semiconductor memory device as claimed in claim 3, characterized in that there is further provided a word line driver coupled to said word line (MWL) for supplying during a read operation an intermediate voltage (V DD /2) when said memory cell (MC) is not selected and the first power source voltage (V DD ) when said memory cell is selected and said first power line (V DD ) is used as said word line and the second power source voltage (V SS ) when said memory cell is selected and said second power line is used as said word line, said intermediate voltage being set between the first and second power source voltages.

Claim 6

The semiconductor memory device as claimed in claim 4, characterized in that said word line driver supplies during a write operation the second power source voltage (V SS ) when said memory cell (MC) is not selected said first power line (V DD ) is used as said word line (MWL) and the first power source voltage when said memory cell is selected and said first power line is used as said word line.

Claim 7

A semiconductor memory device comprising at least one memory cell (MC) having first and second nodes (A, B); and a pair of bit lines (BL, BL ) coupled to said memory cell, characterized in that there are provided: a first power line (V DD ) which is coupled to said memory cell for supplying a first power source voltage (V DD ) ; and a second power line (V SS ) which is coupled to said memory cell for supplying a second power source voltage (V SS ); that said memory cell (MC) includes a first transistor (Q5) connected between said first power line (V DD ) and said first node (A), a second transistor (Q1) coupled between said first node and said second power line (V SS ), a third transistor (Q6) connected between said first power line and said second node (B), a fourth transistor (Q2) coupled between said second node and said second power line, a first capacitor (C1) connected between one of said bit lines and said first node, and a second capacitor (C2) connected between the other of said bit lines and said second node; that said second transistor (Q1) has a gate which is connected to said second node; that said fourth transistor (Q2) has a gate which is connected to said first node; and that one of said first and second power lines (V DD , V SS ) is used in common as a word line (MWL).

Claim 8

A semiconductor memory device comprising at least one memory cell (MC) having first and second nodes (A, B); and a pair of bit lines (BL, BL ) coupled to said memory cell, characterized in that there are provided: a first power line (V DD ) which is coupled to said memory cell for supplying a first power source voltage (V DD ) ; and a second power line (V SS ) which is coupled to said memory cell for supplying a second power source voltage (V SS ); that said memory cell (MC) includes a first transistor (Q5) connected between said first power line (V DD ) and said first node (A), a second transistor (Q1) coupled between said first node and said second power line (V SS ), a third transistor (Q6) connected between said first power line and said second node (B), a fourth transistor (Q2) coupled between said second node and said second power line, a first capacitor (C1) connected between one of said bit lines and said first node, and a second capacitor (C2) connected between the other of said bit lines and said second node; that said second transistor (Q1) has a gate which is connected to said second node; that said fourth transistor (Q2) has a gate which is connected to said first node; and that one of said first and second power lines (V DD , V SS ) is used in common as a word line (MWL).

Claim 9

The semiconductor memory device as claimed in claim 6, characterized in that said first power line (V DD ) supplies the first power source voltage (V DD ) which is a positive voltage and said second power line (V SS ) supplies the second power source voltage (V SS ) which is a negative voltage.

Claim 10

The semiconductor memory device as claimed in claim 6 or 7, characterized in that said first and second transistors (Q5, Q1) form a first complementary metal oxide semiconductor inverter, and said third and fourth transistors (Q6, Q2) form a second complementary metal oxide semiconductor inverter.

Claim 11

The semiconductor memory device as claimed in any of claims 6 to 8, characterized in that there is further provided a sense amplifier (SA) which is connected to said bit lines (BL, BL ), said sense amplifier amplifying a potential difference across said bit lines.

Claim 12

The semiconductor memory device as claimed in claim 9, characterized in that there is further provided a word line driver coupled to said word line (MWL) for supplying during a read operation an intermediate voltage (V DD /2) when said memory cell (MC) is not selected and the first power source voltage (V DD ) when said memory cell is selected and said first power line is used as said word line and the second power source voltage (V SS ) when said memory cell is selected and said second power line is used as said word line, said intermediate voltage being set between the first and second power source voltages.

Claim 13

The semiconductor memory device as claimed in claim 10, characterized in that said word line driver supplies during a write operation the second power source voltage (V SS ) when said memory cell (MC) is not selected said first power line (V DD ) is used as said word line (MWL) and the first power source voltage when said memory cell is selected and said first power line is used as said word line.

Claim 14

The semiconductor memory device as claimed in any of claims 6 to 12, characterized in that there are further provided a first diode (D1) connected between said first node (A) and said second transistor (Q1), and a second diode (D2) connected between said second node (B) and said fourth transistor (Q2).

Claim 15

A semiconductor memory device comprising a plurality of memory cells (MC) each having first and second nodes (A, B) and divided into a plurality of groups, each of said groups including a predetermined number of said memory cells, and a pair of main bit lines (MBL, MBL ) coupled to said memory cells, characterized in that there are provided: a plurality of first power lines (V DD ) which are respectively coupled to said memory cells (MC) for supplying a first power source voltage (V DD ); a plurality of second power lines (V SS ) which are respectively coupled to said memory cells for supplying a second power source voltage (V SS ) ; a plurality of sub bit line pairs (SBL, SBL ) respectively connected to said memory cells, each of said sub bit line pairs being connected to a corresponding one of said groups; a plurality of sub word lines (SWL, SWL ) provided in correspondence with said groups; and transfer gate means (Q G1 -Q G4 ) coupled to said sub word lines for connecting one of said sub bit line pairs to said main bit lines responsive to signals on said sub word lines; that each of said memory cells include a first resistor (R1) connected between one first power line and said first node (A), a first transistor (Q1) connected between said first node and one second power line, a second resistor (R2) connected between said one first power line and said second node (B), a second transistor (Q2) connected between said second node and said one second power line, a first capacitor (C1) connected between one of said bit lines and said first node, and a second capacitor (C2) connected between the other of said bit lines and said second node; that said first transistor (Q1) has a gate which is connected to said second node (B); that said second transistor (Q2) has a gate which is connected to said first node (A); and that one of said one first power line (V DD ) and said one second power line (V SS ) is used in common as a main word line (MWL, MWL ).

Claim 16

A semiconductor memory device comprising a plurality of memory cells (MC) each having first and second nodes (A, B) and divided into a plurality of groups, each of said groups including a predetermined number of said memory cells, and a pair of main bit lines (MBL, MBL ) coupled to said memory cells, characterized in that there are provided: a plurality of first power lines (V DD ) which are respectively coupled to said memory cells (MC) for supplying a first power source voltage (V DD ); a plurality of second power lines (V SS ) which are respectively coupled to said memory cells for supplying a second power source voltage (V SS ) ; a plurality of sub bit line pairs (SBL, SBL ) respectively connected to said memory cells, each of said sub bit line pairs being connected to a corresponding one of said groups; a plurality of sub word lines (SWL, SWL ) provided in correspondence with said groups; and transfer gate means (Q G1 -Q G4 ) coupled to said sub word lines for connecting one of said sub bit line pairs to said main bit lines responsive to signals on said sub word lines; that each of said memory cells include a first resistor (R1) connected between one first power line and said first node (A), a first transistor (Q1) connected between said first node and one second power line, a second resistor (R2) connected between said one first power line and said second node (B), a second transistor (Q2) connected between said second node and said one second power line, a first capacitor (C1) connected between one of said bit lines and said first node, and a second capacitor (C2) connected between the other of said bit lines and said second node; that said first transistor (Q1) has a gate which is connected to said second node (B); that said second transistor (Q2) has a gate which is connected to said first node (A); and that one of said one first power line (V DD ) and said one second power line (V SS ) is used in common as a main word line (MWL, MWL ).

Claim 17

The semiconductor memory device as claimed in claim 13, characterized in that said first power lines (V DD ) supply the first power source voltage (V DD ) which is a positive voltage and said second power lines (V SS ) supply the second power source voltage (V SS ) which is a negative voltage.

Claim 18

The semiconductor memory device as claimed in claim 13 or 14, characterized in that there is further provided a sense amplifier (SA) which is connected to said main bit lines (MBL, MBL ), said sense amplifier amplifying a potential difference across said main bit lines.

Claim 19

The semiconductor memory device as claimed in claim 15, characterized in that there is further provided a word line driver coupled to said main word line (MWL, MWL ) for supplying during a read operation an intermediate voltage (V DD /2) when said memory cells (MC) are not selected and the first power source voltage (V DD ) when said memory cells are selected and said first power line (V DD ) is used as said main word line and the second power source voltage (V SS ) when said memory cells are selected and said second power line (V SS ) is used as said main word line, said intermediate voltage being set between the first and second power source voltages.

Claim 20

The semiconductor memory device as claimed in claim 16, characterized in that said word line driver supplies during a write operation the second power source voltage (V SS ) when said memory cells (MC) are not selected said first power line (V DD ) is used as said main word line (MWL, MWL ) and the first power source voltage (V DD ) when said memory cells are selected and said first power line is used as said main word line.

Claim 21

A semiconductor memory device comprising a plurality of memory cells (MC) each having first and second nodes (MC) and divided into a plurality of groups, each of said groups including a predetermined number of said memory cells, and a pair of main bit lines (MBL, MBL ) coupled to said memory cells, characterized in that there are provided: a plurality of first power lines (V DD which are respectively coupled to said memory cells (MC) for supplying a first power source voltage (V DD ); a plurality of second power lines (V SS which are respectively coupled to said memory cells for supplying a second power source voltage (V SS ); a plurality of sub bit line pairs (SBL, SBL ) respectively connected to said memory cells, each of said sub bit line pairs being connected to a corresponding one of said groups; a plurality of sub word lines (SWL, SWL ) provided in correspondence with said groups; and transfer gate means (Q G1 -Q G4 ) coupled to said sub word lines for connecting one of said sub bit line pairs to said main bit lines responsive to signals on said sub word lines; that each of said memory cells include a first transistor (Q5) connected between one first power line (V DD ) and said first node (A), a second transistor (Q1) connected between said first node and one second power line (V SS ), a third transistor (Q6) connected between said one first power line and said second node (B), a fourth transistor (Q2) connected between said second node and said one second power line, a first capacitor (C1) connected between one of said bit lines and said first node, and a second capacitor (C2) connected between the other of said bit lines and said second node; that said second transistor (Q1) has a gate which is connected to said second node (B); that said fourth transistor (2) has a gate which is connected to said first node (A); and that one of said one first power line (V DD ) and said one second power line (V SS ) is used in common as a main word line (MWL, MWL ).

Claim 22

A semiconductor memory device comprising a plurality of memory cells (MC) each having first and second nodes (MC) and divided into a plurality of groups, each of said groups including a predetermined number of said memory cells, and a pair of main bit lines (MBL, MBL ) coupled to said memory cells, characterized in that there are provided: a plurality of first power lines (V DD which are respectively coupled to said memory cells (MC) for supplying a first power source voltage (V DD ); a plurality of second power lines (V SS which are respectively coupled to said memory cells for supplying a second power source voltage (V SS ); a plurality of sub bit line pairs (SBL, SBL ) respectively connected to said memory cells, each of said sub bit line pairs being connected to a corresponding one of said groups; a plurality of sub word lines (SWL, SWL ) provided in correspondence with said groups; and transfer gate means (Q G1 -Q G4 ) coupled to said sub word lines for connecting one of said sub bit line pairs to said main bit lines responsive to signals on said sub word lines; that each of said memory cells include a first transistor (Q5) connected between one first power line (V DD ) and said first node (A), a second transistor (Q1) connected between said first node and one second power line (V SS ), a third transistor (Q6) connected between said one first power line and said second node (B), a fourth transistor (Q2) connected between said second node and said one second power line, a first capacitor (C1) connected between one of said bit lines and said first node, and a second capacitor (C2) connected between the other of said bit lines and said second node; that said second transistor (Q1) has a gate which is connected to said second node (B); that said fourth transistor (2) has a gate which is connected to said first node (A); and that one of said one first power line (V DD ) and said one second power line (V SS ) is used in common as a main word line (MWL, MWL ).

Claim 23

The semiconductor memory device as claimed in claim 18, characterized in that said first power lines (V DD ) supply the first power source voltage (V DD ) which is a positive voltage and said second power lines (V SS ) supply the second power source voltage (V SS ) which is a negative voltage.

Claim 24

The semiconductor memory device as claimed in claim 18 or 19, characterized in that there is further provided a sense amplifier (SA) which is connected to said main bit lines (MBL, MBL ), said sense amplifier amplifying a potential difference across said main bit lines.

Claim 25

The semiconductor memory device as claimed in claim 20, characterized in that there is further provided a word line driver coupled to said main word line (MWL, MWL ) for supplying during a read operation an intermediate voltage (V DD /2) when said memory cells (MC) are not selected and the first power source voltage (V DD ) when said memory cells are selected and said first power line (V DD ) is used as said main word line and the second power source voltage (V SS ) when said memory cells are selected and said second power line (V SS ) is used as said main word line, said intermediate voltage being set between the first and second power source voltages.

Claim 26

The semiconductor memory device as claimed in claim 21, characterized in that said word line driver supplies during a write operation the second power source voltage (V SS ) when said memory cells (MC) are not selected said first power line (V DD ) is used as said main word line (MWL, MWL ) and the first power source voltage (V DD ) when said memory cells are selected and said first power line is used as said main word line.

Claim 27

The semiconductor memory device as claimed in any of claims 18 to 22, characterized in that there are further provided a first diode (D1) connected between said first node (A) and said second transistor (Q1), and a second diode (D2) connected between said second node (B) and said fourth transistor (Q2).

Claim 28

A semiconductor memory device comprising a plurality of memory cells (MC) each having first and second nodes (A, B); and a pair of bit lines (BL, BL ) coupled to said memory cells, characterized in that there are provided: a first power line (V DD ) which is coupled to said memory cells (MC) for supplying a first power source voltage (V DD ); a second power line (V SS ) which is coupled to said memory cells for supplying a second power source voltage (V SS ); and a plurality of capacitors (C) respectively connected to said bit lines between two adjacent memory cells; that each of said memory cells include a first resistor (R1) connected between said first power line and said first node (A), a first transistor (Q1) connected between said first node and said second power line, a second resistor (R2) connected between said first power line and said second node (B), a second transistor (Q2) connected between said second node and said second power line, a first capacitor (C1) connected between one of said bit lines and said first node, and a second capacitor (C2) connected between the other of said bit lines and said second node; that said first transistor (Q1) has a gate which is connected to said second node (B); that said second transistor (Q2) has a gate which is connected to said first node (A); and that one of said first and second power lines (V DD , V SS ) is used in common as a main word line (MWL).

Claim 29

A semiconductor memory device comprising a plurality of memory cells (MC) each having first and second nodes (A, B); and a pair of bit lines (BL, BL ) coupled to said memory cells, characterized in that there are provided: a first power line (V DD ) which is coupled to said memory cells (MC) for supplying a first power source voltage (V DD ); a second power line (V SS ) which is coupled to said memory cells for supplying a second power source voltage (V SS ); and a plurality of capacitors (C) respectively connected to said bit lines between two adjacent memory cells; that each of said memory cells include a first resistor (R1) connected between said first power line and said first node (A), a first transistor (Q1) connected between said first node and said second power line, a second resistor (R2) connected between said first power line and said second node (B), a second transistor (Q2) connected between said second node and said second power line, a first capacitor (C1) connected between one of said bit lines and said first node, and a second capacitor (C2) connected between the other of said bit lines and said second node; that said first transistor (Q1) has a gate which is connected to said second node (B); that said second transistor (Q2) has a gate which is connected to said first node (A); and that one of said first and second power lines (V DD , V SS ) is used in common as a main word line (MWL).

Claim 30

The semiconductor memory device as claimed in claim 24, characterized in that said first power line (V DD ) supplies the first power source voltage (V DD ) which is a positive voltage and said second power line (V SS ) supplies the second power source voltage (V SS ) which is a negative voltage.

Claim 31

The semiconductor memory device as claimed in claim 24 or 25, characterized in that there is further provided a sense amplifier (SA) which is connected to said bit lines (BL, BL ), said sense amplifier amplifying a potential difference across said bit lines.

Claim 32

A semiconductor memory device comprising a plurality of memory cells (MC) each having first and second nodes (A, B), and a pair of bit lines (BL, BL ) coupled to said memory cells, characterized in that there are provided: a first power line (V DD ) which is coupled to said memory cells (MC) for supplying a first power source voltage (V DD ); a second power line (V SS ) which is coupled to said memory cells for supplying a second power source voltage (V SS ); and a plurality of capacitors (C) respectively connected to said bit lines between two adjacent memory cells; that each of said memory cells include a first transistor (Q5) connected between said first power line and said first node (A), a second transistor (Q1) connected between said first node and said second power line, a third transistor (Q6) connected between said first power line and said second node (B), a fourth transistor (Q2) connected between said second node and said second power line, a first capacitor (C1) connected between one of said bit lines and said first node, and a second capacitor (C2) connected between the other of said bit lines and said second node; that said second transistor (Q1) has a gate which is connected to said second node (B); that said fourth transistor (Q2) has a gate which is connected to said first node (A); and that one of said first and second power lines (V DD , V SS ) is used in common as a main word line (MWL).

Claim 33

A semiconductor memory device comprising a plurality of memory cells (MC) each having first and second nodes (A, B), and a pair of bit lines (BL, BL ) coupled to said memory cells, characterized in that there are provided: a first power line (V DD ) which is coupled to said memory cells (MC) for supplying a first power source voltage (V DD ); a second power line (V SS ) which is coupled to said memory cells for supplying a second power source voltage (V SS ); and a plurality of capacitors (C) respectively connected to said bit lines between two adjacent memory cells; that each of said memory cells include a first transistor (Q5) connected between said first power line and said first node (A), a second transistor (Q1) connected between said first node and said second power line, a third transistor (Q6) connected between said first power line and said second node (B), a fourth transistor (Q2) connected between said second node and said second power line, a first capacitor (C1) connected between one of said bit lines and said first node, and a second capacitor (C2) connected between the other of said bit lines and said second node; that said second transistor (Q1) has a gate which is connected to said second node (B); that said fourth transistor (Q2) has a gate which is connected to said first node (A); and that one of said first and second power lines (V DD , V SS ) is used in common as a main word line (MWL).

Claim 34

The semiconductor memory device as claimed in claim 27, characterized in that said first power line (V DD ) supplies the first power source voltage (V DD ) which is a positive voltage and said second power line (V SS ) supplies the second power source voltage (V SS ) which is a negative voltage.

Claim 35

The semiconductor memory device as claimed in claim 27 or 28, characterized in that there is further provided a sense amplifier (SA) which is connected to said bit lines (BL, BL ), said sense amplifier amplifying a potential difference across said bit lines.