Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
294 words
A memory module of the type formed with a plurality of discrete memory circuits and used to satisfy memory density rquirements greater than that provided by individual circuits mounted thereon, said module comprising: a plurality of discrete data memory circuits each organized to provide an individual string having length equal to an integer multiple of four bits, said circuits arranged to provide a combined data string having a length equal to the sum of the individual string lengths, each circuit including a signal line connected to control transfer of individual data strings; a plurality of data pins each associated with a different bit of the combined data string and connected to transfer a datum, associated with one of the individual strings, from one of the memory circuits for output from said module; a plurality of control pins with each signal line connected to a control pin to receive an external signal for initiating transfer of one of the individual data strings from one of the memory circuits; and an additional memory circuit having a plurality of additional signal lines and a plurality of additional data lines, with a first of the additional signal lines wired in common with the signal line of a first of the data memory circuits to render said additional circuit responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from the first memory circuit; and a second of the additional signal lines wired in common with the signal line of a second of the data memory circuits to render said additional circuit responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from the second memory circuit.
Claim 2
Dependent Claim
294 words
A memory module of the type formed with a plurality of discrete memory circuits and used to satisfy memory density rquirements greater than that provided by individual circuits mounted thereon, said module comprising: a plurality of discrete data memory circuits each organized to provide an individual string having length equal to an integer multiple of four bits, said circuits arranged to provide a combined data string having a length equal to the sum of the individual string lengths, each circuit including a signal line connected to control transfer of individual data strings; a plurality of data pins each associated with a different bit of the combined data string and connected to transfer a datum, associated with one of the individual strings, from one of the memory circuits for output from said module; a plurality of control pins with each signal line connected to a control pin to receive an external signal for initiating transfer of one of the individual data strings from one of the memory circuits; and an additional memory circuit having a plurality of additional signal lines and a plurality of additional data lines, with a first of the additional signal lines wired in common with the signal line of a first of the data memory circuits to render said additional circuit responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from the first memory circuit; and a second of the additional signal lines wired in common with the signal line of a second of the data memory circuits to render said additional circuit responsive to transfer a bit of data along one of the additional data lines when an individual data string is transferred from the second memory circuit.
Claim 3
Dependent Claim
32 words
The module of Claim 1 wherein all of the memory circuits are dynamic random access memory circuits and said additional circuit includes four signal lines which control the transfer of parity data.
Claim 4
Dependent Claim
57 words
The module of Claim 1 wherein the discrete data memory circuits are electrically arranged in pairs to provide a data string length that is an integer multiple of eight bits, said plurality of data memory circuits further arranged to provide a combined data string having a length equal to the sum of the individual data string lengths.
Claim 5
Dependent Claim
83 words
The module of Claim 1 wherein the first of the additional signal lines is wired in common with the signal line of a third one of the data memory circuits to provide a data string length that is a multiple of nine bits and wherein the second of the individual data lines is wired in common with the signal line of a fourth one of the data memory circuits to also provide a data string length that is a multiple of nine bits.
Claim 6
Dependent Claim
24 words
The module of Claim 1 wherein there are an equal number of additional signal lines and additional data lines in the additional memory circuit.
Claim 7
Dependent Claim
18 words
The module of Claim 1 wherein the number of data lines in the additional memory circuit is four.
Claim 8
Dependent Claim
18 words
The module of Claim 1 wherein the number of signal lines in the additional memory circuit is four.
Claim 9
Dependent Claim
28 words
The module of Claim 1 wherein each additional data line is wired to associate a ninth data bit with each of eight bits in the combined data string.
Claim 10
Dependent Claim
28 words
The module of Claim 1 wherein the additional data lines are wired to associate one bit of parity data with every eight bits of the combined data word.