EP0419814A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Pixel protection mechanism for mixed graphics/video display adaptors
Assignee: International Business Machines Corp
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Filing: 1990-08-03
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Granted: —
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Expires: 2010-08-03
Abstract
Abstract A locking mechanism is incorporated in a high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system and two high-resolution frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the high-resolution monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer. The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function. The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.
Inventors
- 👤 Leon Lumelsky
- 👤 Alan W. Peevers
- 👤 Sung Min Choi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 20:06
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/14; G09G5/39; G09G5/395; G09G2340/00; G09G2340/12; G09G2340/125
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
164 words
In a high-resolution video display system including a high-resolution monitor, a computer for providing control signals to said display system, a high-resolution graphics frame buffer for storing computer generated graphics images and supplying said graphics images to the monitor at a rate controlled by said computer generated control signals, and a video data system including a video frame buffer for supplying video data to the monitor under control of said computer the improvement which comprises, an output locking mechanism functionally located between the output of both said frame buffers and the high-resolution monitor including means for preventing predetermined data from one of said buffers from reaching the monitor and overwriting data from the other of said buffers on said monitor screen and, an input locking mechanism including means for preventing static video data stored in predetermined regions of the video frame buffer as defined by an input lock pattern from being overwritten by motion TV data being continually input to said video frame buffer.
Claim 2
Dependent Claim
164 words
In a high-resolution video display system including a high-resolution monitor, a computer for providing control signals to said display system, a high-resolution graphics frame buffer for storing computer generated graphics images and supplying said graphics images to the monitor at a rate controlled by said computer generated control signals, and a video data system including a video frame buffer for supplying video data to the monitor under control of said computer the improvement which comprises, an output locking mechanism functionally located between the output of both said frame buffers and the high-resolution monitor including means for preventing predetermined data from one of said buffers from reaching the monitor and overwriting data from the other of said buffers on said monitor screen and, an input locking mechanism including means for preventing static video data stored in predetermined regions of the video frame buffer as defined by an input lock pattern from being overwritten by motion TV data being continually input to said video frame buffer.
Claim 3
Dependent Claim
31 words
A high-resolution video display system as set forth in claim 1, wherein said output locking mechanism specifically includes means for preventing video data from overwriting graphics data on said monitor screen.
Claim 4
Dependent Claim
92 words
A high-resolution video display system as set forth in claim 2, wherein the output locking mechanism includes, an output lock memory which comprises a reserved bit-plane in the video buffer which stores a predetermined output lock pattern and further including means for utilizing the serial output port of the video frame buffer operating under control of the video frame buffer addressing circuitry in cooperation with combinational logic to disable the output of the video frame buffer and enable the output of the graphics frame buffer on the data path to the monitor.
Claim 5
Dependent Claim
87 words
A high-resolution video display system as set forth in one of claims 1 to 3, wherein the input lock mechanism includes a dynamic random access memory (DRAM) having as many bit storage locations as there are pixels in the video buffer for storing input lock pattern data and means for utilizing said input lock pattern data in conjunction with normal write operations in the video buffer to control the addressing and accessing circuitry of the video frame buffer to disable the accessing function in predetermined regions thereof.
Claim 6
Dependent Claim
88 words
A high-resolution video display system as set forth in claim 3 or claim 4, including means for loading a predetermined display pattern into said output lock memory including, means utilizing the addressing and memory accessing controls of the video frame buffer for sequentially entering predetermined patterns of ones and zeroes provided by a host computer at addresses provided by said host computer and means for inhibiting the writing of any data into pixel data storage locations of said memory while said output lock data is being stored therein.
Claim 7
Dependent Claim
79 words
A high-resolution video display system as set forth in claim 4 or claim 5, further including means for accessing a host computer for loading said DRAM with an input lock data pattern indicative of the region on the monitor on which moving video data is not to be displayed, and means utilizing the addressing circuitry of the video frame buffer to address predetermined regions of said DRAM to store said input lock data patterns in said predetermined regions thereof.
Claim 8
Dependent Claim
194 words
A high-resolution video display system as set forth in one of claims 3 to 6, wherein said output lock memory comprises a plurality of reserved bit planes in the video frame buffer wherein a predetermined bit pattern represents an output lock function and other bit patterns represents "color keys" means utilizing the serial output port of the video frame buffer operating under control of the video frame buffer addressing circuitry operating in the monitor display mode for accessing the output lock bit field of the video frame buffer in parallel with the video data bit field, means for determining if the bit pattern in the output lock represents an "output lock" and if so disabling the output of the video frame buffer and enabling the output of the graphics frame buffer on the data path to the monitor, and if not enabling means for utilizing said bit pattern for accessing a color key table to access a particular "color key" and means utilizing said color key for enabling the display of selected graphics data rather than video data at those pixel locations for which the color of the graphics data matches the "color key".
Claim 9
Dependent Claim
108 words
A high-resolution video display system as set forth in one of claims 3 to 7, wherein said combinational logic includes a "color key" comparator circuit for continuously comparing the color signal accompanying graphics pixel data with a predetermined color key, a successful compare enabling a "graphics output" of a multiplexer circuit means which selectively functions to pass graphics data or video data whereby said graphics data will be displayed on the monitor screen when said multiplexer is so enabled, and further means operable under control of said output lock pattern to enable the graphics output of said multiplexer irrespective of the output of said "color key" comparator circuitry.
Claim 10
Dependent Claim
92 words
A high-resolution video display system as set forth in one of claims 4 to 8, wherein said means for controlling the accessing circuitry of the video frame buffer comprises means operable under control of said input lock pattern data to inhibit the column address strobes (CAS0 and CAS1) in said video frame buffer when the input lock pattern data indicates that a particular pixel within the video frame buffer is to remain unchanged whereby a write operation for any new data supplied to the input of said video buffer will be inhibited.
Claim 11
Dependent Claim
80 words
A high-resolution video display system as set forth in claim 9, wherein said means for controlling the addressing of the video frame buffer comprises means for supplying the same addresses to the DRAM which stores the input lock pattern that are supplied to the video buffer during write operations therein, whereby a particular input lock control bit accessed from the DRAM relates to and controls the writing of data into an associated pixel storage location in the video frame buffer.
Claim 12
Dependent Claim
129 words
A high-resolution video display system as set forth in one of claims 5 to 10, wherein said means for loading the output lock bit plane in said video frame buffer operates at the normal video write rate and includes means for placing a desired output lock pattern on a dedicated position on the input data bus connected to the output lock bit plane of the video frame buffer, and means for inhibiting the video data input to said video frame buffer when it is desired to write only a new pattern into the output lock memory bit plane and for inhibiting the input to the output lock memory plane when new video data is written into the buffer without changing the contents of said output lock memory bit plane.
Claim 13
Dependent Claim
184 words
A high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system, a high-resolution graphics frame buffer for storing computer generated graphics images and supplying said graphics images to the monitor at a rate controlled by said computer generated control signals, and a video data system including a video frame buffer for supplying video data to the monitor under control of said computer the improvement which comprises, an output locking mechanism functionally located between the output of both said frame buffers and the high-resolution monitor including means for preventing predetermined video data from reaching the monitor and overwriting graphics data on said monitor screen with said video data, said output locking mechanism including an output lock memory which comprises a reserved bit-plane in the video buffer which stores a predetermined lock pattern and means for utilizing the serial output port of the video buffer operating under control of the video frame buffer addressing circuitry in combination with combinational logic to disable the output of the video frame buffer and enable the output of the graphics frame buffer.
Claim 14
Dependent Claim
184 words
A high-resolution video display system including a high-resolution monitor, a computer for providing controls signals to said display system, a high-resolution graphics frame buffer for storing computer generated graphics images and supplying said graphics images to the monitor at a rate controlled by said computer generated control signals, and a video data system including a video frame buffer for supplying video data to the monitor under control of said computer the improvement which comprises, an output locking mechanism functionally located between the output of both said frame buffers and the high-resolution monitor including means for preventing predetermined video data from reaching the monitor and overwriting graphics data on said monitor screen with said video data, said output locking mechanism including an output lock memory which comprises a reserved bit-plane in the video buffer which stores a predetermined lock pattern and means for utilizing the serial output port of the video buffer operating under control of the video frame buffer addressing circuitry in combination with combinational logic to disable the output of the video frame buffer and enable the output of the graphics frame buffer.
Claim 15
Dependent Claim
103 words
A high-resolution video display system as set forth in claim 12, wherein said combinational logic includes a "color key" comparator circuit which continuously compares the color signal accompanying graphics data pixel with a predetermined color key, a successful compare enabling a "graphics output" of a multiplexer circuit means which selectively functions to pass graphics data or video data whereby said graphics data will be displayed on the monitor screen when said multiplexer is so enabled, and means operable under control of said output lock pattern to enable the graphics output of said multiplexer irrespective of the output of said "color key" compare circuitry.
Claim 16
Dependent Claim
256 words
In a high-resolution video display system including a high-resolution monitor, a computer for providing control signals to said display system, a igh-resolution graphics frame buffer for storing computer generated graphics images and supplying said graphics images to the monitor at a rate controlled by said computer generated control signals, and a video data system including a video frame buffer for supplying video data to the monitor under control of said computer the improvement which comprises, an input locking mechanism including means for preventing static video data stored in predetermined regions of the video frame buffer from being overwritten by motion TV data being continually input to said video frame buffer, said input lock mechanism including a dynamic random access memory (DRAM) having as many bit storage locations as there are pixels in the video buffer for storing input lock pattern data and means for utilizing said input lock pattern data in conjunction with normal write operations in the video frame buffer to control the addressing and accessing circuitry of the video frame buffer to disable the accessing function in predetermined regions thereof, said means for controlling the accessing circuitry of the video buffer comprising means operable under control of said input lock pattern data to inhibit column address strobes (CAS0, CAS1) in said video frame buffer when the input lock pattern data indicates that a particular pixel within the video frame buffer is to remain unchanged whereby a write operation for any new data supplied to the input of said video frame buffer will be prevented.
Claim 17
Dependent Claim
256 words
In a high-resolution video display system including a high-resolution monitor, a computer for providing control signals to said display system, a igh-resolution graphics frame buffer for storing computer generated graphics images and supplying said graphics images to the monitor at a rate controlled by said computer generated control signals, and a video data system including a video frame buffer for supplying video data to the monitor under control of said computer the improvement which comprises, an input locking mechanism including means for preventing static video data stored in predetermined regions of the video frame buffer from being overwritten by motion TV data being continually input to said video frame buffer, said input lock mechanism including a dynamic random access memory (DRAM) having as many bit storage locations as there are pixels in the video buffer for storing input lock pattern data and means for utilizing said input lock pattern data in conjunction with normal write operations in the video frame buffer to control the addressing and accessing circuitry of the video frame buffer to disable the accessing function in predetermined regions thereof, said means for controlling the accessing circuitry of the video buffer comprising means operable under control of said input lock pattern data to inhibit column address strobes (CAS0, CAS1) in said video frame buffer when the input lock pattern data indicates that a particular pixel within the video frame buffer is to remain unchanged whereby a write operation for any new data supplied to the input of said video frame buffer will be prevented.
References Cited (Backward Citations)
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