EP0418475A2
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EP
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Time switch
Assignee: Mitsubishi Electric Corp
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Filing: 1990-06-06
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Granted: —
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Expires: 2010-06-06
Abstract
Abstract Disclosed herein is a time division switching apparatus for performing the interchange of digital data. According to the first embodiment of the present invention, data to be input from an input highway are input/output simultaneously in parallel to a plurality of buffer memories in the form of parallel data composed of a plurality of bits, and a selector is provided which serves to select n bits out of bits representing parallel data read from the individual buffer memories. According to the second embodiment, respective time switches are provided for each input/output highway, each of the time switches serves to apply data on all the input highways to the buffer memories in parallel, and then to select a desired data from parallel data read in accordance with information stored in a control memory for outputting the selected data to the output highway. According to the third embodiment, if the interchange-unit identifying information outputted from the buffer memory means the interchange of the time slot unit, a signal corresponding to a time slot length is selected from the corresponding buffer memory so as to be delivered to the output highway through a multiplexing circuit, or means the interchange of the bit unit, bit by bit in a predetermined form is selected from a plural of signals read out of the corresponding buffer memory so as to be delivered to the multiplexing circuit. It is thus possible to transmit the quantity of data to be interchanged in large quantities and to perform the interchange of data at a small interchange data unit, or it is feasible to increase the number of highways to be contained. Specifically, the time division switching apparatus can be provided which has the function permitting both of the interchange of the time slot unit and that of the bit unit.
Inventors
- 👤 Takamasa C/O Mitsubishi Denki K.K. Suzuki
- 👤 Takeshi C/O Mitsubishi Denki K.K. Shimpuku
- 👤 Takane C/O Mitsubishi Denki K.K. Kakuno
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 04:28
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/08
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
92 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting data received serially from the input highway to a parallel data; a plurality of time switches for receiving the parallel data and selecting a predetermined portion of the data out of the parallel data; and a multiplexing circuit for receiving the portion of data from the plurality of time switch and converting to a serial data and sending to the output highway.
Claim 2
Dependent Claim
92 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting data received serially from the input highway to a parallel data; a plurality of time switches for receiving the parallel data and selecting a predetermined portion of the data out of the parallel data; and a multiplexing circuit for receiving the portion of data from the plurality of time switch and converting to a serial data and sending to the output highway.
Claim 3
Dependent Claim
87 words
The time division switching apparatus of claim 1, wherein the time switch comprises: a buffer memory for storing the parallel data received from the demultiplexing circuit; a counter for generating a writing address of the buffer memory for storing the parallel data in the buffer memory; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting a predetermined unit of data out of the parallel data read from the buffer memory based on the control information.
Claim 4
Dependent Claim
116 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting data received serially from the input highway to a parallel data at the predetermined parallel data unit; a plurality of time switches for receiving the parallel data and each of the time switch for sending predetermined data out of the parallel data; a counter for generating a writing address of the buffer memory for storing the parallel data in the buffer memory; and a multiplexing circuit or converting data sent by the plurality of time switches to a serial data and sending to the output highway.
Claim 5
Dependent Claim
116 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting data received serially from the input highway to a parallel data at the predetermined parallel data unit; a plurality of time switches for receiving the parallel data and each of the time switch for sending predetermined data out of the parallel data; a counter for generating a writing address of the buffer memory for storing the parallel data in the buffer memory; and a multiplexing circuit or converting data sent by the plurality of time switches to a serial data and sending to the output highway.
Claim 6
Dependent Claim
67 words
The time division switching apparatus of claim 3, wherein the time switch comprises: a buffer memory for storing the parallel data received from the demultiplexing circuit; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting a predetermined unit of data out of the parallel data read from the buffer memory based on the control information.
Claim 7
Dependent Claim
149 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting data received serially from the input highway to a parallel data at the predetermined parallel data unit; a plurality of buffer memories for storing the parallel data received from the demultiplexing circuit; a counter for generating a writing address of the buffer memory for storing the parallel data in the buffer memory; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting a predetermined unit of data out of the parallel data stored in the buffer memory based on the control information; and a multiplexing circuit for converting a plurality of unit of data selected by the selector to a serial data and sending to the output highway.
Claim 8
Dependent Claim
149 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting data received serially from the input highway to a parallel data at the predetermined parallel data unit; a plurality of buffer memories for storing the parallel data received from the demultiplexing circuit; a counter for generating a writing address of the buffer memory for storing the parallel data in the buffer memory; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting a predetermined unit of data out of the parallel data stored in the buffer memory based on the control information; and a multiplexing circuit for converting a plurality of unit of data selected by the selector to a serial data and sending to the output highway.
Claim 9
Dependent Claim
55 words
The time division switching apparatus of claim 2, 4 or 5, wherein the control information includes: a reading writing address of the buffer memory for reading/writing the parallel data from/to the buffer memory; and a select code to be sent to the selector for selecting the predetermined unit of data out of the parallel data.
Claim 10
Dependent Claim
46 words
The time division switching apparatus of claim 6, wherein the data received from the input highway is one bit serial data; the parallel data converted by demultiplexing converter have at least two bits; and the select code is a bit position code of the parallel data.
Claim 11
Dependent Claim
46 words
The time division switching apparatus of claim 1, 2, 3, 4, 5 or 6, wherein the data received from the input highway is an N bits data (N=2,3,4, ...); and the parallel data converted by the demultiplexing circuit have N x P bits data (P=1,2,3,4, ...).
Claim 12
Dependent Claim
68 words
A time division switching apparatus for serially receiving N bits parallel data (N=2,3,4, ...) from an input highway, interchanging a portion of the data and sending data to output highway, comprising: a plurality of time switches responsive to interchange the data, each of which for receiving the N bits parallel data and sending predetermined unit of and predetermined portion of bit/bits out of the N bits parallel data.
Claim 13
Dependent Claim
68 words
A time division switching apparatus for serially receiving N bits parallel data (N=2,3,4, ...) from an input highway, interchanging a portion of the data and sending data to output highway, comprising: a plurality of time switches responsive to interchange the data, each of which for receiving the N bits parallel data and sending predetermined unit of and predetermined portion of bit/bits out of the N bits parallel data.
Claim 14
Dependent Claim
96 words
The time division switching apparatus of claim 9, wherein the time switch comprises: a buffer memory for storing the N bits parallel data received from the input highway; a counter for generating a writing address of the buffer memory for storing the N bits parallel data in the buffer memory; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting predetermined unit of and predetermined position of bit/bits out of the N bits parallel data stored in the buffer memory based on the control information.
Claim 15
Dependent Claim
92 words
A time division switching apparatus for serially receiving N bits parallel data (N=2,3,4 ...) from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a plurality of time switches responsive to interchange the data, each of which is for receiving the N bits data and for sending predetermined number of and predetermined position of bit/bits out of the N bits parallel data; and a counter for generating a writing address of the buffer memory for storing the N bits parallel data in the buffer memory.
Claim 16
Dependent Claim
92 words
A time division switching apparatus for serially receiving N bits parallel data (N=2,3,4 ...) from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a plurality of time switches responsive to interchange the data, each of which is for receiving the N bits data and for sending predetermined number of and predetermined position of bit/bits out of the N bits parallel data; and a counter for generating a writing address of the buffer memory for storing the N bits parallel data in the buffer memory.
Claim 17
Dependent Claim
74 words
The time division switching apparatus of Claim 9, wherein the time switch comprises: a buffer memory for storing the N bits parallel data received from the input highway; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting predetermined unit of and predetermined position of bit/bits out of the N bits parallel data stored in the buffer memory based on the control information.
Claim 18
Dependent Claim
129 words
A time division switching apparatus for serially receiving N bits parallel data (N=2,3,4, ...) from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a plurality of time switches responsive to interchange the data, each of which is for receiving the N bits data and for sending predetermined number and predetermined position of bit/bits out of the N bits parallel data; a counter for generating a writing address of the buffer memory for storing the parallel data in the buffer memory; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting a predetermined unit of data out of the parallel data stored in the buffer memory based on the control information.
Claim 19
Dependent Claim
129 words
A time division switching apparatus for serially receiving N bits parallel data (N=2,3,4, ...) from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a plurality of time switches responsive to interchange the data, each of which is for receiving the N bits data and for sending predetermined number and predetermined position of bit/bits out of the N bits parallel data; a counter for generating a writing address of the buffer memory for storing the parallel data in the buffer memory; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting a predetermined unit of data out of the parallel data stored in the buffer memory based on the control information.
Claim 20
Dependent Claim
63 words
The time division switching apparatus of claim 10, 12 or 13, wherein the control information includes: a reading address of the buffer memory for reading the N bits parallel data stored in the buffer memory; and a select code to be sent to the selector for selecting the predetermined number of and predetermined position of bit/bits out of the N bits parallel data.
Claim 21
Dependent Claim
106 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting N bits data received serially from the input highway to N x P bits parallel data; a plurality of time switches for receiving the N x P bits parallel data and outputting predetermined portion of N bits data out of the N x P parallel data; and a multiplexing circuit for converting N bits data outputted by the plurality of time switches to an N bits unit of serial data and sending to the output highway.
Claim 22
Dependent Claim
106 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting N bits data received serially from the input highway to N x P bits parallel data; a plurality of time switches for receiving the N x P bits parallel data and outputting predetermined portion of N bits data out of the N x P parallel data; and a multiplexing circuit for converting N bits data outputted by the plurality of time switches to an N bits unit of serial data and sending to the output highway.
Claim 23
Dependent Claim
99 words
The time division switching apparatus of claim 15, wherein the time switch comprises: a buffer memory for storing the N x P bits parallel data received from the demultiplexing circuit; a counter for generating a writing address. of the buffer memory for storing the N x P bits parallel data in the buffer memory; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting predetermined portion of N bits data out of the N x P parallel data stored in the buffer memory based on the control information.
Claim 24
Dependent Claim
140 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting N bits data received serially from the input highway to N x P bits parallel data at the predetermined parallel data unit; a plurality of time switches for receiving the N x P bits parallel data and each of the time switch for sending predetermined portion of N bits data out of the N x P parallel data; a counter for generating a writing address of the buffer memory for storing the N x P bits parallel data in the buffer memory; and a multiplexing circuit for converting N bits data sent by the plurality of time switches to N bits of serial data and sending to the output highway.
Claim 25
Dependent Claim
140 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting N bits data received serially from the input highway to N x P bits parallel data at the predetermined parallel data unit; a plurality of time switches for receiving the N x P bits parallel data and each of the time switch for sending predetermined portion of N bits data out of the N x P parallel data; a counter for generating a writing address of the buffer memory for storing the N x P bits parallel data in the buffer memory; and a multiplexing circuit for converting N bits data sent by the plurality of time switches to N bits of serial data and sending to the output highway.
Claim 26
Dependent Claim
76 words
The time division switching apparatus of claim 17, where in the time switch comprises: a buffer memory for storing the N x P bits parallel data received form the demultiplexing circuit; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting predetermined portion of N bits data out of the N x P parallel data stored in the buffer memory based on the control information.
Claim 27
Dependent Claim
166 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting N bits data received serially from the input highway to N x P bits parallel data at the predetermined parallel data unit; a buffer memory for storing the N x P bits parallel data received from the demultiplexing circuit; a counter for generating a writing address of the buffer memory for storing the N x P bits parallel data in the buffer memory; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting predetermined portion of N bits data out of the N x P parallel data stored in the buffer memory based on the control information; and a multiplexing circuit for converting N bits data sent by the plurality of time switches to N bits of serial data and sending to the output highway.
Claim 28
Dependent Claim
166 words
A time division switching apparatus for receiving data from an input highway, interchanging a portion of the data, and sending data to output highway, comprising: a demultiplexing circuit for converting N bits data received serially from the input highway to N x P bits parallel data at the predetermined parallel data unit; a buffer memory for storing the N x P bits parallel data received from the demultiplexing circuit; a counter for generating a writing address of the buffer memory for storing the N x P bits parallel data in the buffer memory; a control memory for storing a control information to read and select the parallel data stored; and a selector for selecting predetermined portion of N bits data out of the N x P parallel data stored in the buffer memory based on the control information; and a multiplexing circuit for converting N bits data sent by the plurality of time switches to N bits of serial data and sending to the output highway.
Claim 29
Dependent Claim
61 words
The time division switching apparatus of claim 16, 18 or 19, wherein the control information includes: a reading address of the buffer memory for reading the N x P bits data stored in the buffer memory; and a select code to be sent to the selector for selecting the N bits data out of the N x P bits parallel data.
Claim 30
Dependent Claim
97 words
A time division switching apparatus for interchanging data received from an input highway between and sending to an output highway, comprising: a plurality of buffer memories for storing the data received from input highway, each of the buffer memory receiving the same data parallelly; access means provided for each buffer memory for reading/writing the data from/to the buffer memory in an either manner of sequential write and random read or random write and sequential read; and selector means provided for each buffer memory for selecting a pre assigned portion of the data stored in the buffer memory.
Claim 31
Dependent Claim
97 words
A time division switching apparatus for interchanging data received from an input highway between and sending to an output highway, comprising: a plurality of buffer memories for storing the data received from input highway, each of the buffer memory receiving the same data parallelly; access means provided for each buffer memory for reading/writing the data from/to the buffer memory in an either manner of sequential write and random read or random write and sequential read; and selector means provided for each buffer memory for selecting a pre assigned portion of the data stored in the buffer memory.
Claim 32
Dependent Claim
72 words
The time division switching apparatus of claim 21, further comprising: a demultiplexing circuit between the input highway and the buffer memories, for converting data serially incoming from the input highway to a parallel data and providing it to the buffer memory; and a multiplexing circuit between the selector and the output highway, for converting the parallel data derived from the selector to a serial data and send it to the output highway.
Claim 33
Dependent Claim
80 words
The time division switching apparatus of claim 21, wherein the access means includes a control information having: an address information for reading/writing the buffer memory, an interchange unit code for identifying a unit to be interchanged, and a selection code for assigning a portion of the data for selection; and the selector means includes: means for identifying the unit to interchanged by receiving the interchange unit code; means for selecting a portion of the data base on the identifying means.
Claim 34
Dependent Claim
131 words
The time division switching apparatus of claim 23, wherein the data is consisted of a plurality of bits and contained in a form of time slot; the buffer memories comprises buffers to store a predetermined number of data corresponding to a predetermined number of time slots; access means provided comprises means for reading/writing the predetermined number of data; and selector means comprises time slot selector means for selecting a data corresponding to a time slot; portion select/assembly means for selecting a portion of a data assigned by the selection code and assembling it to a form of the slot; and switch means for switching the output of the selector means therein between the output of the time slot selector means and the portion select/assembly means based on the interchange unit code.
Claim 35
Dependent Claim
70 words
A time division switch method having time switch for interchanging data therein, comprising the steps of: providing the plurality of the time switches; assigning a control information to each time switch for selecting the portion of the data; parallelly supplying same data to each of the time switch; storing the data supplied in a memory means; selecting the portion of the data from stored data based on the control information;
Claim 36
Dependent Claim
70 words
A time division switch method having time switch for interchanging data therein, comprising the steps of: providing the plurality of the time switches; assigning a control information to each time switch for selecting the portion of the data; parallelly supplying same data to each of the time switch; storing the data supplied in a memory means; selecting the portion of the data from stored data based on the control information;
Claim 37
Dependent Claim
37 words
The time division switch method of claim 25, further comprising the steps of; converting the incoming data to a parallel data before the supplying step; and converting the selected data to a serial data after selecting step.
References Cited (Backward Citations)
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