EP0418457A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Pipelined error checking and correction for cache memories
Assignee: International Business Machines Corp
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Filing: 1990-03-20
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Granted: —
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Expires: 2010-03-20
Abstract
Abstract A scheme for the implementation of single error correction, double error detection function is provided for cache memories wherein the normal cache access time is not affected by the addition of the ECC function. Check bits are provided for multiple bytes of data, thereby lowering the overhead of the error detecting and correcting technique. When a single error is detected, a cycle is inserted by the control circuitry of the cache chip. At the same time, the clocks for the CPU are held high until released by the cache chip on the next cycle. Error correction on multi-byte data is performed using, for example, the 72/64 Hamming code. The technique requires a 2-port cache array (one write port, and one read port). However, the density of a true 2-port array is too low; therefore, the technique is implemented with a 1-port array using a time multiplexing technique, providing an effective 2-port array but with the density of a single port array.
Inventors
- 👤 Hu Herbert Chao
- 👤 Jung-Herng Chang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 18:14
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1064; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0853
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
237 words
A pipelined error checking and correcting cache memory for a central processing unit comprising: a cache array (12); first, second, third, fourth, fifth, sixth, and seventh pipeline registers, said first register (31) storing a mask, said second register (32) being connected to said first register (31) and storing a previous mask, said third register (33) storing a memory address, said fourth register (34) being connected to said third register (33) and storing a previous memory address, said fifth register (35) storing data output from said central processing unit, said sixth register (36) being connected to said fifth register (35) and storing a previous data output, and said seventh register (42) storing an output from said cache memory; first error checking and correcting circuitry (40) connected between an output of said cache memory (12) and said seventh register (42) to generate error flags and corrected data, said corrected data being latched in said seventh register (42); a merge circuit (44) responsive to said second register to merge data latched in said seventh register (42) with data from said central processing unit; and second error checking and correcting circuitry (46) connected between said merge circuit and an input to said cache array (12) to generate check bits for an output of said merge circuit before writing said output with the check bits in the cache array (12) at an address corresponding to a content of said fourth register (34).
Claim 2
Dependent Claim
237 words
A pipelined error checking and correcting cache memory for a central processing unit comprising: a cache array (12); first, second, third, fourth, fifth, sixth, and seventh pipeline registers, said first register (31) storing a mask, said second register (32) being connected to said first register (31) and storing a previous mask, said third register (33) storing a memory address, said fourth register (34) being connected to said third register (33) and storing a previous memory address, said fifth register (35) storing data output from said central processing unit, said sixth register (36) being connected to said fifth register (35) and storing a previous data output, and said seventh register (42) storing an output from said cache memory; first error checking and correcting circuitry (40) connected between an output of said cache memory (12) and said seventh register (42) to generate error flags and corrected data, said corrected data being latched in said seventh register (42); a merge circuit (44) responsive to said second register to merge data latched in said seventh register (42) with data from said central processing unit; and second error checking and correcting circuitry (46) connected between said merge circuit and an input to said cache array (12) to generate check bits for an output of said merge circuit before writing said output with the check bits in the cache array (12) at an address corresponding to a content of said fourth register (34).
Claim 3
Dependent Claim
90 words
The pipelined error checking and correcting cache memory as recited in claim 1 further comprising a first multiplexer (45) responsive to outputs from the cache array and the seventh register (42) and providing one of said outputs to said central processing unit, said first multiplexer (45) selecting the output of said cache array (12) unless an address of in said fourth register (34) is the same as said third register (33) following a store cycle, in which case the output of said seventh register (42) is selected by said multiplexer.
Claim 4
Dependent Claim
31 words
The pipelined error checking and correcting cache memory recited in claim 1 wherein said cache memory has a cache array (12) permitting an effective read and write operation in one cycle.
Claim 5
Dependent Claim
94 words
The pipelined error checking and correcting cache memory recited in claim 3 wherein said cache array comprises: an array of single port static random access memory cells (50, 51, 52, 53) connected to a plurality of bitlines; a single row decoder (54) and first and second column decoders (55, 57) to address said array; and separate input and output lines connected to said bitlines by a plurality of pass transistors, said pass transistors being separately controlled by said first and second column decoders to connect said bitlines to said input and output lines, respectively.
Claim 6
Dependent Claim
99 words
A cache memory array providing an effective two port memory array with the density of a single port array comprising: an array of single port static random access memory cells (50, 51, 52, 53) connected to a plurality of bitlines; a single row decoder (54) and first and second column decoders (55, 57) to address said array; and separate input and output lines connected to said bitlines by a plurality of pass transistors, said pass transistors being separately controlled by said first and second column decoders (55, 57) to connect said bitlines to said input and output lines, respectively.
Claim 7
Dependent Claim
99 words
A cache memory array providing an effective two port memory array with the density of a single port array comprising: an array of single port static random access memory cells (50, 51, 52, 53) connected to a plurality of bitlines; a single row decoder (54) and first and second column decoders (55, 57) to address said array; and separate input and output lines connected to said bitlines by a plurality of pass transistors, said pass transistors being separately controlled by said first and second column decoders (55, 57) to connect said bitlines to said input and output lines, respectively.
References Cited (Backward Citations)
No citation records indexed.
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