EP0417646A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
MOS type semiconductor device with a multilayer gate electrode and method for manufacturing the same
Assignee: Toshiba Corp
•
Filing: 1990-09-06
•
Granted: —
•
Expires: 2010-09-06
Abstract
Abstract A MOS type semiconductor device and a method for the manufacture of the same are disclosed in which a gate electrode (16) is so formed over a semiconductor substrate (11) of a first conductivity type with a gate insulating film (12) formed therebetween as to provide a three-layered structure composed of a first high melting point metal silicide layer (13) formed on the gate insulating film (12), high melting point metal layer (14) formed on the first high melting point metal silicide (13) and a second high melting point metal silicide layer (15) formed on the high melting point metal layer (14). In the gate electrode (16), a length of the first high melting point silicide layer (13) defined in the same direction as that in which a channel region extends is made smaller in length than the high melting point metal layer (14).
Inventors
- 👤 Kouji C/O Intellectual Property Div. Marakami
- 👤 Taira C/O Intellectual Property Div. Matsunaga
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 11:32
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/667; H10D64/668; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01318; H10D64/0132; H10D64/01324
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
170 words
A MOS type semiconductor device comprising: a semiconductor substrate (11) of a first conductivity type: source and drain regions (17, 18) of a second conductivity type formed in a surface portion of the semiconductor substrate; a channel region (19) formed in the surface portion of the semiconductor substrate such that it is situated between the source and drain regions (17, 18); a gate insulating film (12) formed at least on the channel region (19); and a gate electrode (16) comprising a first high melting point metal silicide layer (13) formed on the gate insulating film (12), a high melting metal layer (14) formed on the first high melting point metal silicide layer (13) and a second high melting point metal silicide layer (15) formed on the high melting metal layer (14), in which a length of the first high melting point silicide layer (13) defined in the same direction as that in which the channel region extends is made shorter in length than the high melting point metal layer (14).
Claim 2
Dependent Claim
170 words
A MOS type semiconductor device comprising: a semiconductor substrate (11) of a first conductivity type: source and drain regions (17, 18) of a second conductivity type formed in a surface portion of the semiconductor substrate; a channel region (19) formed in the surface portion of the semiconductor substrate such that it is situated between the source and drain regions (17, 18); a gate insulating film (12) formed at least on the channel region (19); and a gate electrode (16) comprising a first high melting point metal silicide layer (13) formed on the gate insulating film (12), a high melting metal layer (14) formed on the first high melting point metal silicide layer (13) and a second high melting point metal silicide layer (15) formed on the high melting metal layer (14), in which a length of the first high melting point silicide layer (13) defined in the same direction as that in which the channel region extends is made shorter in length than the high melting point metal layer (14).
Claim 3
Dependent Claim
67 words
The MOS type semiconductor device according to claim 1, characterized in that said first and second high melting point silicide layers (13 and 15) are one selected from the group consisting of a molybdenum silicide layer, a titanium silicide layer and tungsten silicide layer and said high melting point metal layer (14) is formed of a material selected from the group consisting of molybdenum, titanium and tungsten.
Claim 4
Dependent Claim
156 words
A MOS type semiconductor device comprising: a semiconductor substrate (11) of a first conductivity type; source and drain regions (17 and 18) of a second conductivity type formed in a surface portion of the semiconductor substrate; a channel region (19) formed in the surface portion of the semiconductor substrate such that it is situated between the source and drain regions (17 and 18); a gage insulating film (12) formed at least on the channel region (19); and a gate electrode (16) composed of a high melting point metal silicide layer (13) formed on the gate insulating film (12) and a high melting point metal layer (14) formed on the high melting point metal silicide layer (13), in which a length of the high melting point metal silicide layer (13) defined in the same direction as that in which the channel region (19) extends is made shorter in length than the high melting point metal layer (14).
Claim 5
Dependent Claim
156 words
A MOS type semiconductor device comprising: a semiconductor substrate (11) of a first conductivity type; source and drain regions (17 and 18) of a second conductivity type formed in a surface portion of the semiconductor substrate; a channel region (19) formed in the surface portion of the semiconductor substrate such that it is situated between the source and drain regions (17 and 18); a gage insulating film (12) formed at least on the channel region (19); and a gate electrode (16) composed of a high melting point metal silicide layer (13) formed on the gate insulating film (12) and a high melting point metal layer (14) formed on the high melting point metal silicide layer (13), in which a length of the high melting point metal silicide layer (13) defined in the same direction as that in which the channel region (19) extends is made shorter in length than the high melting point metal layer (14).
Claim 6
Dependent Claim
66 words
The MOS type semiconductor device according to claim 3, characterized in that said high melting point metal silicide layer (13) is composed of one selected from the group consisting of a molybdenum silicide layer, a titanium silicide layer and a tungsten silicide layer, and said high melting point metal layer (14) is formed of a material selected from the group consisting from molybdenum, titanium and tungsten.
Claim 7
Independent Claim
165 words
A method for manufacturing a MOS type semiconductor device comprising the steps of: forming a gate insulating film (12) on a semiconductor substrate (11) of a first conductivity type; depositing a first high melting point metal silicide layer (13) on the gate insulating film (12); depositing a high melting point metal layer (14) on the first high melting point silicide layer (13); depositing a second high melting point metal silicide layer (15) on the high melting point metal layer (14); and forming a gate electrode (16) by selectively etching the first high melting point metal silicide layer (13), high melting point metal layer (14) and second high melting point metal silicide layer (15), by chemical dry etching in a mixed gas atmosphere of CF₄ and O₂, so that a length of the first high melting point silicide layer (13) defined in the same direction as that in which the channel region extends is made shorter in length than the high melting point metal layer (14).
Claim 8
Independent Claim
165 words
A method for manufacturing a MOS type semiconductor device comprising the steps of: forming a gate insulating film (12) on a semiconductor substrate (11) of a first conductivity type; depositing a first high melting point metal silicide layer (13) on the gate insulating film (12); depositing a high melting point metal layer (14) on the first high melting point silicide layer (13); depositing a second high melting point metal silicide layer (15) on the high melting point metal layer (14); and forming a gate electrode (16) by selectively etching the first high melting point metal silicide layer (13), high melting point metal layer (14) and second high melting point metal silicide layer (15), by chemical dry etching in a mixed gas atmosphere of CF₄ and O₂, so that a length of the first high melting point silicide layer (13) defined in the same direction as that in which the channel region extends is made shorter in length than the high melting point metal layer (14).
Claim 9
Dependent Claim
50 words
The method according to claim 5, further forming source and drain regions (17, 18) in the surface portion of said semiconductor substrate (11) by introducing an impurity of a second conductivity type in the surface portion of the semiconductor substrate (11) with said gate electrode (16) used as a mask.
Claim 10
Dependent Claim
33 words
The method according to claim 5, characterized in that said chemical dry etching is conducted in a gas stream of CF₄ and O₂ at an SCCM of below 300 and below 250, respectively.
Claim 11
Dependent Claim
22 words
The method according to claim 5, characterized in that said etching step is conducted under a high frequency power of over 280W.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.