EP0417013A2
Expired / Lapsed
EP
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Data processor decoding and executing a train of instructions of variable length
Assignee: Fujitsu Ltd
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Filing: 1990-09-07
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Granted: —
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Expires: 2010-09-07
Abstract
Abstract A data processor decoding and executing a train of instructions of variable length. The data processor includes a first instruction control means (1) for temporarily storing a prefetched instruction code (D1) and sequentially outputting said instruction code with units of a predetermined number of bits, and a second instruction control means (2) for decoding an instruction code (D2) fed from the first instruction control means, generating control information (D3) for data processing based on the decoding, and outputting data (D4) indicating instruction update demand quantity to the first instruction control means. On the basis of the data indicating the requested quantity of update instructions, the first instruction control means judges whether it has output a valid instruction code of length exceeding the update demand quantity, and provides an indication (V/INV) of validity or invalidity of the decoded instruction code and controls updating of the instruction code based on a result of the judgement. As a result, it becomes possible to reduce time necessary for the supply of instruction codes and thus improve a data processing speed as the entire processor.
Inventors
- 👤 Akihiro Yoshitake
- 👤 Toshiharu Ohshima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 02:50
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3816; G06F9/30145; G06F9/30149
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
169 words
A data processor decoding and executing a train of instructions of variable length, said data processor comprising: a first instruction control means (1) for temporarily storing a prefetched instruction code (D1) and sequentially outputting said instruction code with units of a predetermined number of bits; and a second instruction control means (2), operatively connected to said first instruction control means, for decoding an instruction code (D2) fed from the first instruction control means, generating control information (D3) for data processing based on the decoding, and outputting data (D4) indicating a requested quantity of update instructions to the first instruction control means, wherein said first instruction control means (1) effects a judgement, based on the data (D4) indicating the requested quantity of update instructions, on whether it has output a valid instruction code of length exceeding the requested quantity of update instructions, and provides an indication (V/INV) of validity or invalidity of the decoded instruction code and controls updating of the instruction code based on a result of the judgement.
Claim 2
Dependent Claim
169 words
A data processor decoding and executing a train of instructions of variable length, said data processor comprising: a first instruction control means (1) for temporarily storing a prefetched instruction code (D1) and sequentially outputting said instruction code with units of a predetermined number of bits; and a second instruction control means (2), operatively connected to said first instruction control means, for decoding an instruction code (D2) fed from the first instruction control means, generating control information (D3) for data processing based on the decoding, and outputting data (D4) indicating a requested quantity of update instructions to the first instruction control means, wherein said first instruction control means (1) effects a judgement, based on the data (D4) indicating the requested quantity of update instructions, on whether it has output a valid instruction code of length exceeding the requested quantity of update instructions, and provides an indication (V/INV) of validity or invalidity of the decoded instruction code and controls updating of the instruction code based on a result of the judgement.
Claim 3
Dependent Claim
106 words
A data processor as set forth in claim 1, wherein, when the first instruction control means (1) judges that it has output a valid instruction code of length exceeding the requested quantity of update instructions, it provides an indication (V) that the decoded instruction code is valid, and updates the instruction code, and when the first instruction control means judges that it has not output a valid instruction code of length exceeding the requested quantity of update instructions, it provides an indication (INV) that the decoded instruction code is invalid, and causes the second instruction control means to effect the decoding again on the identical stage.
Claim 4
Dependent Claim
97 words
A data processor as set forth in claim 2, wherein, said first instruction control means comprises means (31) for storing the prefetched instruction code, means (34) for controlling arrangement of bits of the instruction code to sequentially feed the instruction code with units of the predetermined number of bits to said second instruction control means, and means (36) for judging the validity or invalidity of the instruction code decoded by the second instruction control means, whereby the first instruction control means supplies the second instruction control means with data (DCOVALiD) indicating validity or invalidity of the decoding.
Claim 5
Dependent Claim
102 words
A data processor as set forth in claim 2, wherein said second instruction control means comprises means (44) for computing the requested quantity of update instructions, means (41,42,43,45) for decoding instruction code information, addressing information and additional information included in the train of instructions of variable length, and a control means (46) for forming a current decoding stage of instruction codes and sequentially selecting each of the outputs of the computing means and decoding means according to the decoding stage, whereby the second instruction control means supplies the first instruction control means with data (RQHW) indicating the requested quantity of update instructions.
Claim 6
Dependent Claim
56 words
A data processor as set forth in claim 4, wherein said second instruction control means further comprises means (41a∼5a, 41b∼45b), responsive to control clocks (φ1, φ3) from said control means , for latching each information to be input to the computing means and decoding means and each information output from said computing means and decoding means.
Claim 7
Dependent Claim
24 words
A data processor as set forth in claim 5, wherein said computing means and decoding means are constituted by a programmable logic array (600).
References Cited (Backward Citations)
No citation records indexed.
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