Programmable logic device and storage circuit used therewith

Claim 2

A programmable logic device comprising: data storage means (20, 20′) for storing 1-bit control data; at least one data line (24, 25) for transmitting data to be stored in said data storage means; a select line (28) for transmitting a select signal for selecting said data storage means; MOS-type switch means (10) responsive to the stored data in said data storage means to be switch controlled; two signal lines (11, 12) coupled to each other through said MOS-type switch means; and potential amplitude enlarging means (41, 42, 43) for making the potential amplitude of data stored in said data storage means larger than the potential ampli­tude of a signal transmitted over said two signal lines.

Claim 3

A programmable logic device according to claim 1, characterized in that said potential amplitude enlarging means includes supply voltage switching means (43) for selectively outputting one of a first supply voltage (V DD ) and a second supply voltage (V PP ) to said data storage means.

Claim 4

A programmable logic device according to claim 1, characterized in that said potential amplitude enlarging means includes voltage generating means (42) for raising said first supply voltage (V DD ) to generate said second supply voltage (V PP ).

Claim 5

A programmable logic device according to claim 1, characterized in that said data storage device is of a CMOS structure having an N type well region (92) which is supplied with an output potential of said supply voltage switching means.

Claim 6

A programmable logic device according to claim 2, characterized in that said supply voltage switching means outputs to said data storage means said first supply voltage when data is written into said data storage means and said second supply voltage when said MOS-type switch means is rendered conductive.

Claim 7

A programmable logic device according to claim 1, characterized in that said data storage means comprises a flip-flop (23) and at least one select MOS transistor (26, 27) having its source-to-drain path connected between said flip-flop and said data line and its gate connected to said select line.

Claim 8

A programmable logic device according to claim 6, characterized in that said flip-flop comprises two inverters (21, 22) which are anti-parallel con­nected.

Claim 9

A programmable logic device according to claim 7, characterized in that each of said inverters is a CMOS inverter.

Claim 10

A programmable logic device comprising: a programmable logic device cell array in which a plurality of programmable logic device cells are arrayed in a matrix, each of said programmable logic device cells having data storage means (20, 20′) for storing 1-bit control data, at least one data line (24, 25) for transmitting data to be stored in said data storage means, and a MOS-type switch means (10) responsive to stored data in said data storage means to be switch controlled, data lines (24, 25) for a plurality of programmable logic device cells arrayed in a first direction being made common to each other, select lines (28) for a plurality of programmable logic device cells arrayed in a second direction intersecting said first direction being made common to each other, a plurality of MOS type switch means (10) for a plurality of programmable logic device cells being connected in series; and potential amplitude enlarging means (41, 42, 43) provided for said plurality of programmable logic device cells for enlarging the potential amplitude of data stored in said data storage means.

Claim 11

A programmable logic device comprising: a programmable logic device cell array in which a plurality of programmable logic device cells are arrayed in a matrix, each of said programmable logic device cells having data storage means (20, 20′) for storing 1-bit control data, at least one data line (24, 25) for transmitting data to be stored in said data storage means, and a MOS-type switch means (10) responsive to stored data in said data storage means to be switch controlled, data lines (24, 25) for a plurality of programmable logic device cells arrayed in a first direction being made common to each other, select lines (28) for a plurality of programmable logic device cells arrayed in a second direction intersecting said first direction being made common to each other, a plurality of MOS type switch means (10) for a plurality of programmable logic device cells being connected in series; and potential amplitude enlarging means (41, 42, 43) provided for said plurality of programmable logic device cells for enlarging the potential amplitude of data stored in said data storage means.

Claim 12

A programmable logic device according to claim 9, characterized in that said potential amplitude enlarging means includes supply voltage switching means (43) for selectively outputting one of a first supply voltage (V DD ) and a second supply voltage (V PP ) to said data storage means.

Claim 13

A programmable logic device according to claim 9, characterized in that said potential amplitude enlarging means includes voltage generating means (42) for raising said first supply voltage (V DD ) to generate said second supply voltage (V PP ).

Claim 14

A programmable logic device according to claim 9, characterized in that said data storage device is of a CMOS structure having an N type well region (92) which is supplied with an output potential of said supply voltage switching means.

Claim 15

A programmable logic device according to claim 10, characterized in that said supply voltage switching means outputs to said data storage means said first supply voltage when data is written into said data storage means and said second supply voltage when said MOS-type switch means is rendered conductive.

Claim 16

A storage circuit comprising: data storage means (23) for storing data on a first and a second level in a pair; a data line (25) for transmitting data to be written into said data storage means; a select line (28) for transmitting a select signal to select said data storage means; and power supply means (71, 72, 73, 74) for supplying a supply voltage (V FF ) having a magnitude smaller than a potential amplitude of data or a signal transmitted over said data line and said select line in writing data on said first level into said data storage means.

Claim 17

A storage circuit comprising: data storage means (23) for storing data on a first and a second level in a pair; a data line (25) for transmitting data to be written into said data storage means; a select line (28) for transmitting a select signal to select said data storage means; and power supply means (71, 72, 73, 74) for supplying a supply voltage (V FF ) having a magnitude smaller than a potential amplitude of data or a signal transmitted over said data line and said select line in writing data on said first level into said data storage means.

Claim 18

A programmable logic device comprising: data storage means (23) for storing data at a first and a second level in a pair; a data line (25) for transmitting data to be written into said data storage means; a select line (28) for transmitting a select signal to select said data storage means; MOS-type switch means (10) responsive to stored data in said data storage means to be switch controlled; two signal lines (11, 12) coupled by said MOS-type switch means; and power supply means (71, 72, 73, 74) for supplying to said data storage means a supply voltage (V FF ) having a magnitude smaller than the potential amplitude of data or signals transmitted over said data line and said select line in writing data at said first level into said data storage means, and supplying to said data storage means a supply voltage (V PP ) having a magnitude larger than the potential amplitude of data or signals transmitted over said data line and said select line in switch controlling said MOS type switch means.

Claim 19

A programmable logic device comprising: data storage means (23) for storing data at a first and a second level in a pair; a data line (25) for transmitting data to be written into said data storage means; a select line (28) for transmitting a select signal to select said data storage means; MOS-type switch means (10) responsive to stored data in said data storage means to be switch controlled; two signal lines (11, 12) coupled by said MOS-type switch means; and power supply means (71, 72, 73, 74) for supplying to said data storage means a supply voltage (V FF ) having a magnitude smaller than the potential amplitude of data or signals transmitted over said data line and said select line in writing data at said first level into said data storage means, and supplying to said data storage means a supply voltage (V PP ) having a magnitude larger than the potential amplitude of data or signals transmitted over said data line and said select line in switch controlling said MOS type switch means.

Claim 20

A programmable logic device comprising: a programmable logic device cell array in which a plurality of programmable logic device cells are arrayed in a matrix, each of said programmable logic device cells having data storage means (20, 20′) for storing data at first and second levels in a pair, one data line (25) for transmitting data to be stored in said data storage means, a select line (28) for transmitting a select signal to select said data storage means and a MOS-type switch means (10) responsive to stored data in said data storage means to be switch controlled, data lines (25) for a plurality of programmable logic device cells arrayed in a first direction being made comnon to each other, select lines (28) for a plurality of programmable logic device cells arrayed in a second direction intersecting said first direction being made common to each other, a plurality of MOS type switch means (10) for a plurality of programmable logic device cells being connected in series; and power supply means (71, 72, 73, 74) provided for said plurality of programmable logic device cells for supplying a power supply voltage to said data storage means.

Claim 21

A programmable logic device comprising: a programmable logic device cell array in which a plurality of programmable logic device cells are arrayed in a matrix, each of said programmable logic device cells having data storage means (20, 20′) for storing data at first and second levels in a pair, one data line (25) for transmitting data to be stored in said data storage means, a select line (28) for transmitting a select signal to select said data storage means and a MOS-type switch means (10) responsive to stored data in said data storage means to be switch controlled, data lines (25) for a plurality of programmable logic device cells arrayed in a first direction being made comnon to each other, select lines (28) for a plurality of programmable logic device cells arrayed in a second direction intersecting said first direction being made common to each other, a plurality of MOS type switch means (10) for a plurality of programmable logic device cells being connected in series; and power supply means (71, 72, 73, 74) provided for said plurality of programmable logic device cells for supplying a power supply voltage to said data storage means.

Claim 22

A programmable logic device according to claim 16, characterized in that said power supply means includes power switching means (72, 73) for outputting a supply voltage (V FF ) of a magnitude smaller than the magnitude of data or a signal transmitted over said data line and said select line in writing data into said data storage means of each of said plurality of programmable logic device cells and a supply voltage (V PP ) of a magnitude larger than the magnitude of data or a signal transmitted over said data line and said select line in reading data.

Claim 23

A programmable logic device according to claim 17, characterized in that said data storage device of each of said programmable logic device cells is of a CMOS structure having an N type well region (92) which is supplied with an output potential of said power switching means (72, 73).