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EP0415737A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Motion detecting circuits for video images

Assignee: Sony Corp
•
Filing: 1990-08-29
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Granted: —
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Expires: 2010-08-29
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Abstract

Abstract A motion detecting circuit separates picture data of one frame into a plurality of image segments. The circuit includes a first memory (2) for receiving current frame image data and a second memory (3) for receiving previous or one frame delayed image data. Each of the first and second memories (2, 3) comprises a plurality of memory areas (A, B) separated into two blocks, each individual memory area (A, B) storing picture data for one image segment. The two memory blocks (A, B) are operative in alternating fashion in reading and writing picture data. A plurality of arithmetic circuits (9 to 12) are associated with the memory areas (A, B) to receive therefrom the picture data of each image segment and process the received picture data for deriving a motion vector of each individual image segment.

Inventors

  • 👤 Naohisa C/O Patents Division Kitazato

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 17:56
CPC Classifications
G; G06; G06T; G06T7/00; G06T7/20; H; H04; H04N; H04N19/00; H04N19/42; H04N19/43; H04N19/433; G06T7/223; G06T7/238; H04N19/50; H04N19/503; H04N19/51

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 94 words
A motion detecting circuit for a video image, the circuit comprising: a first buffer memory (2) for storing current image picture data separated into plurality of first component data representative of current image segments; a second buffer memory (3) for storing previous image picture data separated into a plurality of second component data representative of previous image segments; and a plurality of arithmetic means (9 to 12) for deriving motion vectors, each of said arithmetic means (9 to 12) receiving the first component data and corresponding second component data for deriving the motion vectors.
Claim 2
Dependent Claim 94 words
A motion detecting circuit for a video image, the circuit comprising: a first buffer memory (2) for storing current image picture data separated into plurality of first component data representative of current image segments; a second buffer memory (3) for storing previous image picture data separated into a plurality of second component data representative of previous image segments; and a plurality of arithmetic means (9 to 12) for deriving motion vectors, each of said arithmetic means (9 to 12) receiving the first component data and corresponding second component data for deriving the motion vectors.
Claim 3
Dependent Claim 34 words
A circuit according to claim 1 wherein each of said arithmetic means (9 to 12) comprises an absolute differential value calculating means (13), an accumulating circuit (14) and a minimum value detecting circuit (15).
Claim 4
Dependent Claim 29 words
A circuit according to claim 1 wherein said first buffer memory (2) stores current frame image data and said second buffer memory (3) stores one frame delayed image data.
Claim 5
Dependent Claim 35 words
A circuit according to claim 1 which further comprises a multiplexer (16) connected to outputs of the plurality of arithmetic means (9 to 12), and an output buffer memory (17) connected to said multiplexer (16).
Claim 6
Dependent Claim 38 words
A circuit according to claim 4 which further comprises a first address change-over circuit (8) connected to said first second buffer memories (2, 3), and a second address change-over circuit (20) connected to said output buffer memory (17).
Claim 7
Dependent Claim 22 words
A circuit according to claim 5 which further comprises a controller (7) connected to said first and second change-over circuits (8, 20).
Claim 8
Dependent Claim 19 words
A circuit as according to claim 6 wherein said controller (7) is supplied with a video signal synchronization signal.

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