Electrical circuit

Claim 2

A circuit comprising a differential input stage (10) and a separate single ended output stage (12,16), bias means (Q9,R1,R2) for establishing bias currents in the input and output stages; characterised by a first current mirror (Q10,Q11) including an input current path (Q11) and an output current path (Q10), means for connecting the input current path to the output stage and for connecting the output current path to the input stage, whereby a bias current (Is) in the input stage is controllable relative to a bias current (I2) in the output stage.

Claim 3

A circuit according to claim 1, wherein the input stage (10) comprises first and second current paths (Q1,Q2); the output stage (12,16) comprises third and fourth current paths (Q3,Q5; Q4,Q6); the bias means (Q9,R1,R2) is adapted to establish bias currents (I s ,I2) in the first, second, third and fourth current paths; and wherein connecting means is adapted to supply the input current (Q11) with the combined bias currents of the third and fourth current paths, and the output current path (Q10) with the combined bias currents of the first and second current paths.

Claim 4

A circuit according to claim 2, wherein the input stage (10) comprises first and second transistors (Q1,Q2) arranged as a differential amplifier; the output stage comprises third and fourth transistors (Q3,Q4); a first resistor (R1) being provided for connecting an input of the first transistor (Q1) and an output of the third transistor (Q3) to a voltage source (Vcc); a second resistor (R2) being provided for connecting an input of the second transistor (Q2) and an output of the fourth transistor (Q4) to the voltage source (Vcc); wherein the bias means (Q9) is adapted to establish equal bias currents (I1) in the first and second resistors (R1,R2); the first current mirror comprising seventh and eighth transistors (Q10,Q11); the output stage comprising a second current mirror (16) including fifth and sixth transistors (Q5,Q6) connected to the third and fourth transistors (Q3,Q4); wherein the eighth transistor (Q11) of the second current mirror is arranged as a diode and is connected to the first current mirror (16) for receiving the combined input currents of the third and fourth transistors (Q3,Q4); and the seventh transistor (Q10) is connected to the outputs of the first and second transistors (Q1,Q2).

Claim 5

A circuit according to claim 3, wherein one or more of the transistors comprises emitter, collector and base terminals; the emitter terminal being the output, the collector terminal being the input and the base terminal the common terminal.