Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
77 words
A self calibrating circuit comprising: a clock generating clock cycles of a selected frequency, a current generator, a pair of transistors, each transistor being coupled in parallel to the other and in series with said generator and with a respective capacitor, each of said pair of transistors being coupled to said clock, and means of selectively charging and discharging one of said capacitors in a time period less the time period of one of said clock cycles.
Claim 2
Dependent Claim
77 words
A self calibrating circuit comprising: a clock generating clock cycles of a selected frequency, a current generator, a pair of transistors, each transistor being coupled in parallel to the other and in series with said generator and with a respective capacitor, each of said pair of transistors being coupled to said clock, and means of selectively charging and discharging one of said capacitors in a time period less the time period of one of said clock cycles.
Claim 3
Dependent Claim
18 words
The circuit of claim 1 wherein said transistors and said capacitors are created in the same semiconductor chip.
Claim 4
Dependent Claim
12 words
The circuit of claim 1 wherein said capacitors of different capacitive value.
Claim 5
Dependent Claim
12 words
The circuit of claim 1 wherein said capacitors are of equal value.
Claim 6
Dependent Claim
15 words
The circuit of claim 1 wherein there is further provided means for discharging the capacitors.
Claim 7
Dependent Claim
16 words
The circuit of claim 1 wherein one of said transistors is directly connected to said clock.
Claim 8
Dependent Claim
17 words
The current of claim 6 wherein there is further provided clock driven means for discharging said capacitors.
Claim 9
Dependent Claim
33 words
The circuit of claim 1 wherein one of said transistors is coupled to and driven by the clock and the other of said transistors is selectively latched into or out of said circuit.
Claim 10
Dependent Claim
23 words
The circuit of claim 1 wherein there is further provided an operational amplifier coupled to said transistor and to a reference voltage source.
Claim 11
Dependent Claim
18 words
The circuit of claim 1 wherein said current generator comprises means for producing current over varying time sequences.
Claim 12
Dependent Claim
20 words
The circuit of claim 10 wherein there is further provided means for stepping said current generator through said time sequences.
Claim 13
Dependent Claim
101 words
A circuit for generating timing edges within a clock cycle comprising: clock means, means for generating a controlled current, and a ratio circuit coupled to said clock means and said generating means, said ratio circuit comprising at least two capacitors, each of said capacitors being coupled in series with a respective transistor, each of said capacitor transistor series being coupled in parallel between said controlled current generating means and ground, said clock means being directly coupled to the control electrode of one of said transistors, means for selectively turning off the other of said transistors, and means for discharging said capacitors.
Claim 14
Dependent Claim
101 words
A circuit for generating timing edges within a clock cycle comprising: clock means, means for generating a controlled current, and a ratio circuit coupled to said clock means and said generating means, said ratio circuit comprising at least two capacitors, each of said capacitors being coupled in series with a respective transistor, each of said capacitor transistor series being coupled in parallel between said controlled current generating means and ground, said clock means being directly coupled to the control electrode of one of said transistors, means for selectively turning off the other of said transistors, and means for discharging said capacitors.