EP0414361A2
Expired / Lapsed
EP
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Semiconductor antifuse structure and method
Assignee: Advanced Micro Devices Inc
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Filing: 1990-07-10
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Granted: —
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Expires: 2010-07-10
Abstract
Abstract A method for forming an array of antifuse structures on a semiconductor substrate which previously has had CMOS devices fabricated thereupon up to first metallization. A fuse structure is formed as a sandwich by successively depositing a bottom layer of TiW (16), a layer of amorphous silicon (18), and a top layer of TiW (20). The amorphous silicon is formed in an antifuse via formed in a dielectric layer (17) covering the bottom layer of TiW (16). First metallization (22) is deposited and patterned over the top layer of TiW. An intermetal dielectric layer is formed over the fuse array and second metal conductors are formed thereupon. An alternative embodiment includes forming an oxide sidewall spacer around the periphery of an anti fuse structure. Connection resistance to the bottom layer of TiW is lowered by using a number of vias between the second--metal conductors and the bottom layer of TiW in a row of an array of antifuse devices.
Inventors
- 👤 Kathryn E. Gordon
- 👤 Chin S. Jenq
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 18:21
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
321 words
A method of forming an array of antifuse structures on a semiconductor substrate having circuit elements formed thereon, comprising the steps of: providing a semiconductor substrate which has been processed with CMOS process steps up to but not including first metallization; depositing a first layer of TiW over said substrate, including over said circuit elements; masking and etching said first layer of TiW to provide TiW bottom conductors for said array of antifuses and to leave a protective layer of TiW over said circuit elements; forming a first dielectric layer over said first layer of TiW; masking and etching away portions of said first dielectric layer to define an array of fuse vias in said first dielectric layer and to define connection vias for connection of said first layer of TiW to subsequently deposited second metal conductors by exposing portions of said first layer of TiW; removing the first dielectric layer over the protective layer of TiW over said circuit elements; depositing a layer of antifuse silicon over said first dielectric layer and over said exposed portions of said first layer of TiW; depositing a second layer of TiW over said layer of antifuse silicon; masking and etching away portions of said second TiW layer and said layer of antifuse silicon to define an array of fuses; forming a protective photoresist layer over said array of fuses and removing said protective TiW layer over said circuit elements; depositing a first-metal conductor over said second layer of TiW, said circuit elements, and said connection vias; forming an intermetal dielectric layer over said first metal conductor; forming vias in said intermetal dielectric layer to said first metal conductor; forming second-metal conductors over said intermetal dielectric layer to provide a plurality of connections between said second metal conductors and said first layer of TiW to reduce connection resistance to said antifuse structures; and forming a passivation layer over the surface of the semiconductor substrate.
Claim 2
Independent Claim
321 words
A method of forming an array of antifuse structures on a semiconductor substrate having circuit elements formed thereon, comprising the steps of: providing a semiconductor substrate which has been processed with CMOS process steps up to but not including first metallization; depositing a first layer of TiW over said substrate, including over said circuit elements; masking and etching said first layer of TiW to provide TiW bottom conductors for said array of antifuses and to leave a protective layer of TiW over said circuit elements; forming a first dielectric layer over said first layer of TiW; masking and etching away portions of said first dielectric layer to define an array of fuse vias in said first dielectric layer and to define connection vias for connection of said first layer of TiW to subsequently deposited second metal conductors by exposing portions of said first layer of TiW; removing the first dielectric layer over the protective layer of TiW over said circuit elements; depositing a layer of antifuse silicon over said first dielectric layer and over said exposed portions of said first layer of TiW; depositing a second layer of TiW over said layer of antifuse silicon; masking and etching away portions of said second TiW layer and said layer of antifuse silicon to define an array of fuses; forming a protective photoresist layer over said array of fuses and removing said protective TiW layer over said circuit elements; depositing a first-metal conductor over said second layer of TiW, said circuit elements, and said connection vias; forming an intermetal dielectric layer over said first metal conductor; forming vias in said intermetal dielectric layer to said first metal conductor; forming second-metal conductors over said intermetal dielectric layer to provide a plurality of connections between said second metal conductors and said first layer of TiW to reduce connection resistance to said antifuse structures; and forming a passivation layer over the surface of the semiconductor substrate.
Claim 3
Independent Claim
299 words
A method of forming an array of antifuse structures on a semiconductor substrate having circuit elements formed thereon, comprising the steps of: providing a semiconductor substrate which has been processed with CMOS process steps up to but not including first metallization; depositing a first layer of TiW over said substrate, including over said circuit elements; masking and etching said first layer of TiW to provide TiW bottom conductors for said array of antifuses and to leave a protective layer of TiW over said circuit elements; forming a first dielectric layer over said first layer of TiW; masking and etching away portions of said first dielectric layer to define an array of fuse vias in said first dielectric layer; removing the first dielectric layer over the protective layer of TiW over said circuit elements; depositing a layer of antifuse silicon over said first dielectric layer and over said exposed portions of said first layer of TiW; depositing a second layer of TiW over said layer of antifuse silicon; masking and etching away portions of said second TiW layer and said layer of antifuse silicon to define an array of fuses; forming a protective photoresist layer over said array of fuses and removing said protective TiW layer over said circuit elements; depositing a first-metal conductor over said second layer of TiW, said circuit elements, and said connection vias; forming an intermetal dielectric layer over said first metal conductor; forming vias in said intermetal dielectric layer to said first metal conductor and to said first TiW layer; forming second-metal conductors over said intermetal dielectric layer to provide a plurality of connections between said second metal conductors and said first layer of TiW to reduce connection resistance to said antifuse structures; and forming a passivation layer over the surface of the semiconductor substrate.
Claim 4
Independent Claim
299 words
A method of forming an array of antifuse structures on a semiconductor substrate having circuit elements formed thereon, comprising the steps of: providing a semiconductor substrate which has been processed with CMOS process steps up to but not including first metallization; depositing a first layer of TiW over said substrate, including over said circuit elements; masking and etching said first layer of TiW to provide TiW bottom conductors for said array of antifuses and to leave a protective layer of TiW over said circuit elements; forming a first dielectric layer over said first layer of TiW; masking and etching away portions of said first dielectric layer to define an array of fuse vias in said first dielectric layer; removing the first dielectric layer over the protective layer of TiW over said circuit elements; depositing a layer of antifuse silicon over said first dielectric layer and over said exposed portions of said first layer of TiW; depositing a second layer of TiW over said layer of antifuse silicon; masking and etching away portions of said second TiW layer and said layer of antifuse silicon to define an array of fuses; forming a protective photoresist layer over said array of fuses and removing said protective TiW layer over said circuit elements; depositing a first-metal conductor over said second layer of TiW, said circuit elements, and said connection vias; forming an intermetal dielectric layer over said first metal conductor; forming vias in said intermetal dielectric layer to said first metal conductor and to said first TiW layer; forming second-metal conductors over said intermetal dielectric layer to provide a plurality of connections between said second metal conductors and said first layer of TiW to reduce connection resistance to said antifuse structures; and forming a passivation layer over the surface of the semiconductor substrate.
Claim 5
Independent Claim
224 words
A method of forming an anti fuse structure comprising the steps of: providing a silicon substrate which has been processed with CMOS process steps through contact formation and which has circuit elements formed thereon; forming a protective layer over the circuit elements; masking and etching said protective layer away from a fuse area; depositing a first layer of TiW over said fuse area; depositing a layer of antifuse silicon material over said first layer of TiW; depositing a second layer of TiW over said layer of antifuse silicon material; masking and etching said first layer of TiW, said layer of antifuse silicon material, and said second layer of TiW to form a TiW-Si-TiW antifuse sandwich; depositing an oxide layer and etching a sidewall spacer from said oxide layer around the periphery of said TiW-Si-TiW anti fuse sandwich; removing the protective layer; depositing a layer of first conductor material over said second layer of TiW and over said circuit elements; etching portions of the layer of the first conductor material and said second layer of TiW; forming a planarized dielectric layer over said substrate; forming a via mask and etching standard vias to said layer of first conductor material and etching pick-up vias to said first layer of TiW; and depositing and etching a layer of a second conductor material over said planarized dielectric layer.
Claim 6
Independent Claim
224 words
A method of forming an anti fuse structure comprising the steps of: providing a silicon substrate which has been processed with CMOS process steps through contact formation and which has circuit elements formed thereon; forming a protective layer over the circuit elements; masking and etching said protective layer away from a fuse area; depositing a first layer of TiW over said fuse area; depositing a layer of antifuse silicon material over said first layer of TiW; depositing a second layer of TiW over said layer of antifuse silicon material; masking and etching said first layer of TiW, said layer of antifuse silicon material, and said second layer of TiW to form a TiW-Si-TiW antifuse sandwich; depositing an oxide layer and etching a sidewall spacer from said oxide layer around the periphery of said TiW-Si-TiW anti fuse sandwich; removing the protective layer; depositing a layer of first conductor material over said second layer of TiW and over said circuit elements; etching portions of the layer of the first conductor material and said second layer of TiW; forming a planarized dielectric layer over said substrate; forming a via mask and etching standard vias to said layer of first conductor material and etching pick-up vias to said first layer of TiW; and depositing and etching a layer of a second conductor material over said planarized dielectric layer.
Claim 7
Dependent Claim
14 words
The method of Claim 3 wherein said protective layer is a layer of TiW.
Claim 8
Dependent Claim
11 words
The method of Claim 3 wherein said protective layer is aluminum.
Claim 9
Dependent Claim
28 words
The method of Claim 3 including the step of depositing a layer of a barrier metal prior to depositing the layer of first conductor material over circuit elements.
Claim 10
Dependent Claim
15 words
The method of Claim 3 wherein said antifuse silicon is a layer of amorphous silicon.
Claim 11
Dependent Claim
178 words
An anti fuse structure formed on a semiconductor substrate, comprising: a semiconductor substrate; a first layer of TiW formed on a first portion of the surface of said semiconductor substrate; a layer of a first dielectric material formed on said first layer of TiW, said layer of first dielectric material having a first opening formed therein to expose a first portion of the first layer of TiW; a layer of antifuse silicon formed over said first portion of the first layer of TiW and over portions of said layer of first dielectric material which are near said first opening; a second layer of TiW formed over said layer of antifuse silicon; a first metal conductor formed over said second layer of TiW; wherein said dielectric layer has a second opening formed therein to expose a second portion of the first layer of TiW and wherein a second metal layer is formed to connect to said second portion of the first layer of TiW through said second opening to provide lower connection resistance to said first layer of TiW.
Claim 12
Dependent Claim
178 words
An anti fuse structure formed on a semiconductor substrate, comprising: a semiconductor substrate; a first layer of TiW formed on a first portion of the surface of said semiconductor substrate; a layer of a first dielectric material formed on said first layer of TiW, said layer of first dielectric material having a first opening formed therein to expose a first portion of the first layer of TiW; a layer of antifuse silicon formed over said first portion of the first layer of TiW and over portions of said layer of first dielectric material which are near said first opening; a second layer of TiW formed over said layer of antifuse silicon; a first metal conductor formed over said second layer of TiW; wherein said dielectric layer has a second opening formed therein to expose a second portion of the first layer of TiW and wherein a second metal layer is formed to connect to said second portion of the first layer of TiW through said second opening to provide lower connection resistance to said first layer of TiW.
Claim 13
Dependent Claim
111 words
The antifuse structure of Claim 8: including a plurality of antifuse structures formed in an array on the semiconductor substrate, wherein the respective first metal conductors for each device are arranged as strips extending and arranged generally parallel to each other; including a strip of a first layer of TiW extending generally perpendicular to and spaced apart from said first metal strips wherein respective anti fuse devices are located between and at crossover regions of said first metal conductors and said strip of first TiW; and wherein a plurality of second openings are provided to said strip of said first layer of TiW to reduce connection resistance to said antifuse structures.
Claim 14
Dependent Claim
128 words
An antifuse structure comprising: a semiconductor substrate; a first layer of TiW formed on said semiconductor substrate; a layer of antifuse silicon formed on said first layer of TiW; a second layer of TiW formed on said layer of antifuse silicon, said first and second layers of TiW and said layer of antifuse silicon forming a vertical antifuse sandwich structure; a sidewall spacer formed adjacent to and surrounding the periphery of said antifuse sandwich structure; a first metal layer overlying said sidewall spacer and said anti fuse sandwich structures; an intermetal dielectric layer formed over said first metal layer; and a second metal connected to the first TiW layer through a via formed in said intermetal dielectric layer to provide reduced connection resistance to said first TiW layer.
Claim 15
Dependent Claim
128 words
An antifuse structure comprising: a semiconductor substrate; a first layer of TiW formed on said semiconductor substrate; a layer of antifuse silicon formed on said first layer of TiW; a second layer of TiW formed on said layer of antifuse silicon, said first and second layers of TiW and said layer of antifuse silicon forming a vertical antifuse sandwich structure; a sidewall spacer formed adjacent to and surrounding the periphery of said antifuse sandwich structure; a first metal layer overlying said sidewall spacer and said anti fuse sandwich structures; an intermetal dielectric layer formed over said first metal layer; and a second metal connected to the first TiW layer through a via formed in said intermetal dielectric layer to provide reduced connection resistance to said first TiW layer.
Claim 16
Dependent Claim
18 words
The antifuse structure of Claim 10 wherein said layer of antifuse silicon includes a layer of amorphous silicon.
References Cited (Backward Citations)
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