EP0412701A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Thin film transistor and preparation thereof
Assignee: Canon Inc
•
Filing: 1990-07-30
•
Granted: —
•
Expires: 2010-07-30
Abstract
Abstract A thin film transistor has a semiconductor layer region sandwiched between first insulating layer region and second insulating layer region, and a control electrode provided on the semiconductor layer region via said second insulating layer region. The semiconductor layer region has a channel region and plurality of main electrode regions of impurity concentration higher than that of the channel region. An interface between at least one of said plurality of main electrode regions and said channel region has a sectional structure which is more remote from the control electrode side in the direction from the second insulating layer region side toward the first insulating layer region.
Inventors
- 👤 Toru C/O Canon Kabushiki Kaisha Koizumi
- 👤 Jun C/O Canon Kabushiki Kaisha Nakayama
- 👤 Hidemasa C/O Canon Kabushiki Kaisha Mizutani
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 14:53
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/0323; H10D30/0327; H10D30/60; H10D30/601; H10D30/605; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; H10D30/6719; H10D30/6758; H10D30/6759; H10D62/117; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
108 words
A thin film transistor having a semiconductor layer region sandwiched between first insulating layer region and second insulating layer region, and a control electrode provided on said semiconductor layer region via said second insulating layer region, wherein said semiconductor layer region has a channel region and plurality of main electrode regions of impurity concentration higher than that of said channel region, and an interface between at least one of said plurality of main electrode regions and said channel region has a sectional structure which is more remote from said control electrode side in the direction from said second insulating layer region side toward said first insulating layer region.
Claim 2
Dependent Claim
108 words
A thin film transistor having a semiconductor layer region sandwiched between first insulating layer region and second insulating layer region, and a control electrode provided on said semiconductor layer region via said second insulating layer region, wherein said semiconductor layer region has a channel region and plurality of main electrode regions of impurity concentration higher than that of said channel region, and an interface between at least one of said plurality of main electrode regions and said channel region has a sectional structure which is more remote from said control electrode side in the direction from said second insulating layer region side toward said first insulating layer region.
Claim 3
Dependent Claim
76 words
A thin film transistor according to claim 1, wherein said plurality of main electrode regions include respectively first semiconductor regions and second semiconductor region of an impurity concentration higher than that of the first semiconductor region, and an interface between said first and second semiconductor regions has a sectional structure which is more remote from said control electrode side in the direction from said second insulating layer region side toward said first insulating layer region side.
Claim 4
Dependent Claim
63 words
A thin film transistor according to claim 1, wherein said semiconductor layer region is arranged so that an interface between the other of said plurality of main electrode regions and said channel region has a sectional structure which is more closer to said control electrode side in the direction from said second insulating layer region side toward said first insulating layer region side.
Claim 5
Dependent Claim
63 words
A thin film transistor according to claim 1, wherein said semiconductor layer region is arranged so that also an interface between the other of said plurality of main electrode regions and said channel region has a sectional structure which is more remote from said control electrode region in the direction from said second insulating layer region side toward said first insulating layer region.
Claim 6
Dependent Claim
20 words
A thin film transistor according to claim 1, wherein a sectional area of said channel region has a rhomboid configuration.
Claim 7
Dependent Claim
20 words
A thin film transistor according to claim 1, wherein a sectional area of said channel region has a trapezoid configuration.
Claim 8
Dependent Claim
25 words
A thin film transistor according to claim 1, wherein a sectional area of said channel region has a configuration of a trapezoid with equal legs.
Claim 9
Dependent Claim
19 words
A thin film transistor according to claim 1, wherein said semiconductor layer region is formed by single crystalline silicon.
Claim 10
Dependent Claim
19 words
A thin film transistor according to claim 1, wherein said semiconductor layer region is formed by non-single crystalline silicon.
Claim 11
Dependent Claim
73 words
A thin film transistor according to claim 1, wherein with a position of said interface immediately beneath said second insulating layer region has as a original point, when a layer thickness of said semiconductor layer region is made T SOI and a maximum displacement of said semiconductor layer region in the direction normal to a layer thickness direction is L UP , a value of L UP /T SOI is 0.35 and more.
Claim 12
Dependent Claim
28 words
Method for manufacturing a thin film transistor of claim 1, comprising: obliquely implanting impurity into the interface between said semiconductor layer region and said second insulating layer region.
Claim 13
Dependent Claim
22 words
Method for manufacturing a thin film transistor according to claim 11, wherein said impurity implanting is achieved by an ion implantation process.
Claim 14
Dependent Claim
63 words
Method of manufacturing thin film transistor according to claim 12, wherein said ion implantation process satisfies a relationship: X ≦ R x · tan ϑ₂ ≦ X + L wherein ϑ₂ is an ion injection angle, R X a mask thickness, L a length of said control electrode, and X a length of an aperture defined by said control electrode and said mask.
Claim 15
Dependent Claim
29 words
Method for manufacturing a thin film transistor of claim 1, comprising producing said main electrode region after formation of an oblique surface corresponding to said interface by anisotropic etching.
Claim 16
Dependent Claim
19 words
Method for manufacturing a thin film transistor according to claim 14, wherein said anisotropic etching is reactive ion etching.
Claim 17
Dependent Claim
24 words
An electronic circuit device comprising a thin film transistor of claim 1, and a photoelectric conversion element integrally formed together on a common substrate.
Claim 18
Dependent Claim
23 words
An electronic circuit device comprising a thin film transistor of claim 1 and a liquid crystal cell driven by said thin film transistor.
Claim 19
Dependent Claim
45 words
An information processing apparatus comprising: an electronic circuit device wherein a thin film transistor of claim 1 and a photoelectric conversion element are provided integrally on a common substrate; means for maintaining an original at a reading position; and light source for illuminating the original.
Claim 20
Dependent Claim
41 words
An information processing apparatus comprising: an electronic circuit device having a thin film transistor of claim 1 and a liquid crystal cell driven by said thin film transistor; and means for outputting signal to be inputted into said electronic circuit device.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.