EP0412247A2
Expired / Lapsed
EP
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Cache memory system
Assignee: International Business Machines Corp
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Filing: 1990-05-09
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Granted: —
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Expires: 2010-05-09
Abstract
Abstract A cache memory system develops an optimum sequence for transferring data values between a main memory (50) and a line buffer (30) internal to the cache (20). At the end of a line transfer, the data in the line buffer (30) is written into the cache memory (20) as a block. Following an initial cache miss, the cache memory system monitors the sequence of data requests received for data in the line that is being read in from main memory (50). If the sequence being used to read in the data causes the processor (10) to wait for a specific data value in the line, a new sequence is generated in which the specific data value is read at an earlier time in the transfer cycle. This sequence is associated with the instruction that caused the first miss and is used for subsequent misses caused by the instruction. If, in the process of handling a first miss related to a specific instruction, a second miss occurs which is caused by the same instruction but which is for data in a different line of memory, the sequence associated with the instruction is marked as an ephemeral miss. Data transferred to the line buffer (30) in response to an ephemeral miss is not stored in the cache memory (20) and limited to that portion of the line accessed within the line buffer (30).
Inventors
- 👤 Philip George Emma
- 👤 Joshua Wilson Knight
- 👤 James Herbert Pomerene
- 👤 Thomas Roberts Puzak
- 👤 Rudolph Nathan Rechtschaffen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 13:05
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F2212/00; G06F2212/60; G06F2212/6024
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
136 words
Method of responding to a memory access request, generated by the processor executing an instruction, for a data value not found in the cache memory wherein the requested data value resides in the main memory of a computer system, characterized by the steps of: (a) transferring elements of a line of N data values, including the requested data value, according to a first sequence, from the main memory (50) to the cache memory (20) in response to the memory access request; (b) monitoring the order in which data values in said line are requested by the processor (10) to define a second sequence; and (c) transferring the elements of the line of data values, according to the second sequence, from the main memory to the cache memory in response to a subsequent execution of the instruction.
Claim 2
Dependent Claim
136 words
Method of responding to a memory access request, generated by the processor executing an instruction, for a data value not found in the cache memory wherein the requested data value resides in the main memory of a computer system, characterized by the steps of: (a) transferring elements of a line of N data values, including the requested data value, according to a first sequence, from the main memory (50) to the cache memory (20) in response to the memory access request; (b) monitoring the order in which data values in said line are requested by the processor (10) to define a second sequence; and (c) transferring the elements of the line of data values, according to the second sequence, from the main memory to the cache memory in response to a subsequent execution of the instruction.
Claim 3
Dependent Claim
178 words
Method set forth in claim 1, characterized in that the cache memory (20) includes a line buffer (30) and a storage element and the step (a) includes the steps of: transferring the elements of the line of N data values to a line buffer (30) according to said first sequence; and transferring the N data values from said line buffer to said storage element; the step (b) includes the steps of: monitoring access requests for data values in said line of N data values while the elements of said line of N data values are being transferred to said line buffer (30); identifying which of said access requests are for data values that are not available in the line buffer (30) at the time the data values are requested; and setting a wait state in response to said identification; and the step (c) includes the step of transferring the elements of said line of N data values from the main memory to the line buffer (30) according to the second sequence only if the wait state was set.
Claim 4
Dependent Claim
62 words
Method set forth in claim 1 or 2, characterized in that the step (b) includes the steps of: identifying which of said N data values are requested by the processor (10) while the line of N data values is transferred from the main memory (50) to the cache memory (20); and recording indicators representing the identified data values as said second sequence.
Claim 5
Dependent Claim
83 words
Method set forth in claim 1 or 2, characterized by steps of: (d) identifying any instruction which initiates a request for data values in a second line of data values while a first line of data values is being transferred from said main memory to said cache memory in response to a prior execution of said identified instruction; and (e) inhibiting the transfer of data values from said line buffer to said storage element in response to subsequent executions of said identified instruction.
Claim 6
Dependent Claim
76 words
Method set forth in claim 1 or 2, characterized in that step (b) comprises the step of storing, in a table, an command entry for each respective instruction that initiates a request for a target data value not found in cache memory, each of said command entries containing said second sequence for the respective instruction, representing a preferred sequence for retrieving data values in the line of data values that includes the respective target data value.
Claim 7
Dependent Claim
32 words
Method set forth in claim 5, characterized in, that the table of commands representing the preferred sequences for transferring memory words from the main memory to the cache memory is set associative.
Claim 8
Dependent Claim
103 words
Method set forth in claim 1 or 2, characterized by steps of: (d) detecting a second memory access request for a data value not found in the cache memory (20) and not contained in the current line being transferred from the main memory (50); (e) interrupting transfer of said current line from the main memory (50) to the line buffer (30); (f) responding to said second memory access request for data values not found in the cache memory according to steps (a), (b), and (c); and (g) completing the transfer of current line from the main memory (50) to the line buffer (30).
Claim 9
Dependent Claim
157 words
Method of responding to multiple memory access requests for a target data value not found in a cache memory wherein the requested data value resides in a main memory, characterized by steps of: (a) transferring a line of data values, including the target data value from the main memory (50) to the cache memory (20) according to a first sequence in response to a first one of said multiple memory requests for said target data value; (b) monitoring data value requests received by said cache memory (20) to determine a second sequence representing an order in which a subset of the data values in said line are requested from said cache memory; and (c) transferring the subset of data values in the line according to the second sequence and then transferring the remaining data values in the line in a predetermined sequence, in response to a subsequent one of said multiple requests for the target data value.
Claim 10
Dependent Claim
157 words
Method of responding to multiple memory access requests for a target data value not found in a cache memory wherein the requested data value resides in a main memory, characterized by steps of: (a) transferring a line of data values, including the target data value from the main memory (50) to the cache memory (20) according to a first sequence in response to a first one of said multiple memory requests for said target data value; (b) monitoring data value requests received by said cache memory (20) to determine a second sequence representing an order in which a subset of the data values in said line are requested from said cache memory; and (c) transferring the subset of data values in the line according to the second sequence and then transferring the remaining data values in the line in a predetermined sequence, in response to a subsequent one of said multiple requests for the target data value.
Claim 11
Dependent Claim
183 words
Method for responding to a plurality of memory access requests for data values in respectively different lines of data values, wherein said plurality of memory access requests are generated in response to a single instruction being executed by said processor at a respective plurality of different times, of a computer system including a processor, a main memory (50), having multiple lines of data values, and a cache memory (20), having a line buffer (30), characterized by steps of: (a) transferring the data values in one of said plurality of lines from said main memory (50) to the line buffer (30) of said cache memory (20), responsive to a respective execution of said single instruction; (b) setting an indicator if a further execution of said single instruction, accessing a data value in a further one of said plurality of lines, is detected during the transfer of data values in said one line from said main memory (50) to said line buffer; (c) inhibiting any transfer of data from said line buffer (30) to said cache memory (20) in response to said indicator being set.
Claim 12
Dependent Claim
183 words
Method for responding to a plurality of memory access requests for data values in respectively different lines of data values, wherein said plurality of memory access requests are generated in response to a single instruction being executed by said processor at a respective plurality of different times, of a computer system including a processor, a main memory (50), having multiple lines of data values, and a cache memory (20), having a line buffer (30), characterized by steps of: (a) transferring the data values in one of said plurality of lines from said main memory (50) to the line buffer (30) of said cache memory (20), responsive to a respective execution of said single instruction; (b) setting an indicator if a further execution of said single instruction, accessing a data value in a further one of said plurality of lines, is detected during the transfer of data values in said one line from said main memory (50) to said line buffer; (c) inhibiting any transfer of data from said line buffer (30) to said cache memory (20) in response to said indicator being set.
Claim 13
Dependent Claim
116 words
Method as set forth in one of the claims 1-9, characterized by (a) transferring the target data value from the main memory (50) to the line buffer (30) in response to the memory access request; (b) examining a second instruction, which follows the first instruction, for a potential memory access request for a data value in the same line as said target data value, to determine a next data value in said line to transfer from said main memory (50) to said line buffer (30); and (c) transferring any next data value determined in step (b) from the main memory (50) to the line buffer (30) as the next data value after the target data value.
Claim 14
Dependent Claim
121 words
Method as set forth in one of the claims 1-10, characterized by steps of: (a) transferring the line of data values according to a first sequence, from the main memory (50) to a line buffer (30) in response to a first one of the memory access requests; (b) monitoring said memory access requests to determine which data values in said line are requested; and (c) defining a second sequence in which the data values are transferred from the main memory (50) to the line buffer (30) for subsequent memory access requests so that the data values in the line which are requested by said memory access requests are transferred before the data values in said line which are not so requested.
Claim 15
Dependent Claim
161 words
Computer system including a processor, a cache memory and a main memory, apparatus for responding to a memory access request, generated by the processor executing an instruction, for a data value not found in the cache memory wherein the requested data value resides in the main memory, operating with a method as set forth in one of the claims 1-11, characterized by means for transferring elements of a line of N data values, including the requested data value, according to a first sequence, from the main memory (50) to the cache memory (20) in response to the memory access request; by means for monitoring the order in which data values in said line are requested by the processor (10) to define a second sequence; and by means for transferring the elements of the line of data values, according to the second sequence, from the main memory (50) to the cache memory (20) in response to a subsequent execution of the instruction.
Claim 16
Dependent Claim
122 words
Computer system as set forth in claim 12, characterized by means for transferring the data values in one of said plurality of lines from said main memory (50) to the line buffer (30) of said cache memory (20), responsive to a respective execution of said single instruction; by means for setting an indicator if a further execution of said single instruction, accessing a data value in a further one of said plurality of lines, is detected during the transfer of data values in said one line from said main memory (50) to said line buffer (30); and by means for inhibiting any transfer of data from said line buffer (30) to said cache memory (20) in response to said indicator being set.
References Cited (Backward Citations)
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