Demodulated data recognition and decision device

Claim 2

A demodulated data recognition and decision device comprising a detector demodulation circuit for demodulating an input signal and outputting a base band signal; a comparator for determining a binary value of said base band signal and outputting the binary signal; a clock recovery circuit for reproducing a recovered clock signal having the same frequency as that of a bit rate of transmitted data and generating a higher rate clock signal than said recovered clock signal; multi-timing decision means for sampling said binary signal with said higher rate clock signal, performing a majority rule decision operation for a plurality of values corresponding to a plurality of points of the sampled binary signal, and outputting a value obtained through said majority rule decision operation; and a latch circuit for latching the value output by said multi-timing decision means with said recovered clock signal and outputting the latched value as a demodulated digital data.

Claim 3

A demodulated data recognition and decision device according to Claim 1, wherein the multi-timing decision means comprises a shift register for sampling said binary signal with said higher rate clock signal and shifting the sampled values in sequence, and a majority rule circuit for receiving predetermined outputs of a plurality of stages of the parallel outputs of said shift register and outputting values decided under majority rule of these output values of a plurality of stages to said latch circuit.

Claim 4

A demodulated data recognition and decision device according to Claim 1, wherein the multi-timing decision means comprises an A/D converter for converting said base band signal into a multi-value quantized signal, a shift register for sampling said multi-value quantized signal with said higher rate clock signal and shifting the sampled values in sequence, an adder for receiving predetermined outputs from a plurality of stages of parallel outputs of said shift register and adding these outputs from said plurality of stages, and a comparator for comparing an added value output by said adder with a predetermined threshold value and outputting a binary data signal corresponding to a relation of value between the added value and the threshold value to said latch circuit.

Claim 5

A demodulated data recognition and decision device according to Claim 1, wherein said the multi-­timing decision means comprises a shift register for sampling said binary signal with said higher rate clock signal and shifting a sampled value in sequence, said shift register outputting parallel outputs from a predetermined plurality of stages, a plurality of data selectors for receiving said outputs of said shift register and each selectively outputting a digital value from sets of values, said digital value corresponding to a binary value of said binary signal, an adder for adding said digital values output from said plurality of data selectors, and a comparator for comparing the added values output by said adder with a predetermined threshold value and outputting binary data corresponding to a relation between the added value and the threshold value to said latch circuit.

Claim 6

A demodulated data recognition and decision device according to Claim 4, wherein said sets of values comprises a set of digital values having higher values than other sets of values and wherein said set of digital values having higher values corresponds to a central point of said digital values outputted from said plurality of data selectors.

Claim 7

A demodulated data recognition and decision device comprising a detector demodulation circuit for demodulating an input signal and outputting a base band signal; a comparator for determining a binary value of said base band signal and outputting a corresponding binary signal; a clock recovery circuit for reproducing a recovered clock signal having the same frequency as a bit rate of said input signal and producing a higher rate clock signal relative to said recovered clock signal; a shift register for sampling said binary signal with said higher rate clock signal and shifting a sampled value in sequence, said shift register outputting predetermined parallel outputs of a plurality of stages; a latch circuit for latching said predetermined parallel outputs with each of said recovered clock signals; and a majority rule circuit for outputting the value decided under majority rule of the values output by said latch circuit as a demodulated digital data.

Claim 8

A demodulated data recognition and decision device comprising a detector demodulation circuit for demodulating an input signal and outputting a base band signal; a comparator for determining a binary value of said base band signal and outputting a corresponding binary signal; a clock recovery circuit for reproducing a recovered clock signal having the same frequency as a bit rate of said input signal and producing a higher rate clock signal relative to said recovered clock signal; a shift register for sampling said binary signal with said higher rate clock signal and shifting a sampled value in sequence, said shift register outputting predetermined parallel outputs of a plurality of stages; a latch circuit for latching said predetermined parallel outputs with each of said recovered clock signals; and a majority rule circuit for outputting the value decided under majority rule of the values output by said latch circuit as a demodulated digital data.

Claim 9

A demodulated data recognition and decision device according to Claims 2 to 6, wherein the plurality of predetermined stages of the shift register comprise three stages.

Claim 10

A demodulated data recognition and decision device comprising a detector demodulation circuit for demodulating an input signal and outputting a base band signal; a comparator for determining a binary signal; a clock recovery circuit for reproducing a recovered clock signal having the same frequency as a bit rate of a transmitted data, and generating a higher rate clock signal than said recovered clock signal, said clock recovery circuit receiving a lag signal or a lead signal, instantaneously advancing a phase of said recovered clock signal in response to said lag signal, and instantaneously delaying a phase of said recovered clock signal in response to said lead signal; and a multi-timing decision means for sampling said binary signal with said higher rate clock signal, performing majority rule for a plurality of values received from said means for sampling, outputting the values obtained from said performing of majority rule and outputting said lag signal or said lead signal when the sampling occurs at a position displaced from the control position of said base band signal.

Claim 11

A demodulated data recognition and decision device comprising a detector demodulation circuit for demodulating an input signal and outputting a base band signal; a comparator for determining a binary signal; a clock recovery circuit for reproducing a recovered clock signal having the same frequency as a bit rate of a transmitted data, and generating a higher rate clock signal than said recovered clock signal, said clock recovery circuit receiving a lag signal or a lead signal, instantaneously advancing a phase of said recovered clock signal in response to said lag signal, and instantaneously delaying a phase of said recovered clock signal in response to said lead signal; and a multi-timing decision means for sampling said binary signal with said higher rate clock signal, performing majority rule for a plurality of values received from said means for sampling, outputting the values obtained from said performing of majority rule and outputting said lag signal or said lead signal when the sampling occurs at a position displaced from the control position of said base band signal.

Claim 12

A demodulated data recognition and decision device according to Claim 8, wherein the multi-timing decision means comprises a shift register for sampling said binary signal with said higher rate clock signal and shifting the sampled value in sequence, majority rule circuits for receiving each of a plurality of sets of outputs of a plurality of predetermined stages of parallel outputs of said shift register, said majority rule circuits outputting each value decided under majority rule for every set of said plurality of sets so as to be installed in correspondence with said plurality of sets; a latch circuit for latching the output values of said majority rule circuits with said recovered clock signal; and a detector circuit for receiving output values of said latch circuit and outputting either said lag signal or lead signal.

Claim 13

A demodulated data recognition and decision device according to Claim 9, wherein said plurality of sets of outputs comprises a central set(,a forward set and a rearward set), the value corresponding to the central set of said plurality of sets of the output values of said latch circuit is output as said digital data.

Claim 14

A demodulated data recognition and decision device according to Claim 10, wherein each of said plurality of sets is constituted by parallel outputs of three stages of said shift register.

Claim 15

A demodulated data recognition and decision device according to Claim 10 or 11, wherein said plurality of sets are three sets.

Claim 16

A demodulated data recognition and decision device according to Claim 12, wherein the detector circuit outputs a lag signal when a received value corresponding to the set including the nearest stage from an input side of said shift register is different from a value corresponding to the other two sets, and outputs the lead signal when the value corresponding to the set including a farthest stage from the input side of said shift register is different from other two values.