Non-volatile semiconductor memory device having an improved testing mode of operation and method of forming checkerwise test pattern in memory cell array

Claim 1

A non-volatile semiconductor memory device comprising a) a plurality of word lines (W0 to W31), b) a plurality of bit lines (BL0 to BL7) defining a plurality of locations in combination with said word lines, c) a memory cell array (3) having a plurality of non-­volatile memory cells (3-1 to 3-256) respectively disposed at said locations and memorizing pieces of data information in a rewriteable manner, respectively, d) a row address decoder circuit (1) responsive to an address signal indicative of a row address for selectively activating at least one of said word lines, e) a column address decoder circuit (2) responsive to an address signal indicative of a column address for se­lecting at least one of said bit lines, and f) data means (4 to 9) for selectively carrying out erasing, write-in and read-out operations on at least one of said non-volatile memory cells located at the location defined by said one of said word lines in combination with said one of said bit lines, characterized in that said row address decoder circuit has means (1af to 1aj; 51aa and lag to 1aj) for concurrently activating at least every second word line in the presence of a test signal (CTS) if said row address signal is indicative of a first state, and in that said means of said row address decoder circuit concur­rently activate another group of said word lines in the presence of said test signal when said row address signal is indicative of a second state, wherein said data means carry out at least said erase and write-in operations on a plurality of said non-volatile memory cells coupled to said word lines to be activated in the presence.: of said test signal.

Claim 3

A method of forming a checkerwise test pattern in a plurality of non-volatile memory cells arranged in rows and columns incorporated in a non-volatile semiconductor memory device, said non-volatile memory device further comprising a plurality of word lines for concurrently activating the rows of said non-volatile memory cells, respectively, and data means for erasing and writing pieces of data informa­tion from and into said plurality of non-volatile memory cells, characterized by the steps of: a) driving all of said word lines for activating all of said non-volatile memory cells; b) concurrently erasing pieces of data information previously memorized in said non-volatile memory cells; c) concurrently writing first pieces of data informa­tion into all of said non-volatile memory cells; d) driving every second word lines for activating said non-volatile memory cells coupled to every second word line; e) concurrently erasing said first pieces of data information from said non-volatile memory cells coupled to every second word line; and f) concurrently writing second pieces of data informa­tion into said non-volatile memory cells coupled to every second word line, in which each of said first pieces of data information is indicated by a first bit string differ­ent from a second bit string indicative of each of said second pieces of data information.

Claim 4

A method of forming a checkerwise test pattern in a plurality of non-volatile memory cells arranged in rows and columns incorporated in a non-volatile semiconductor memory device, said non-volatile memory device further comprising a plurality of word lines for concurrently activating the rows of said non-volatile memory cells, respectively, and data means for erasing and writing pieces of data informa­tion from and into said plurality of non-volatile memory cells, characterized by the steps of: a) driving all of said word lines for activating all of said non-volatile memory cells; b) concurrently erasing pieces of data information previously memorized in said non-volatile memory cells; c) concurrently writing first pieces of data informa­tion into all of said non-volatile memory cells; d) driving every second word lines for activating said non-volatile memory cells coupled to every second word line; e) concurrently erasing said first pieces of data information from said non-volatile memory cells coupled to every second word line; and f) concurrently writing second pieces of data informa­tion into said non-volatile memory cells coupled to every second word line, in which each of said first pieces of data information is indicated by a first bit string differ­ent from a second bit string indicative of each of said second pieces of data information.