EP0408032A2
Expired / Lapsed
EP
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Data output control circuit for semiconductor storage device
Assignee: Toshiba Corp
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Filing: 1990-07-12
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Granted: —
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Expires: 2010-07-12
Abstract
Abstract An equalizing transistor is connected between first and second data lines (d, d ) to which a data corresponding to a data stored in a memory cell (MS) selected by an address is outputted. When the equalizing pulse (Φ) is applied to the control terminal of equalizing transistor, the first and second data lines (d, d ) are made conductive with respect to each other so that the data lines (d, d ) are set at a predetermined equal potential. Output buffer switch has first and second output switch (M1, M2) connected in series between a power source supply terminal and ground. An interconnection node (N1) between the output switch (M1, M2) is a data output terminal. One and the other of the pair of data lines (d, d ) are connected to the control nodes (N4, N5) of the first and second output switch. Data line switch (B1, B2) is connected between the equalizing transistor (M3) and the output buffer switch at at least one of the pair of data lines (d, d ). The data line switch is turned on and off by the equalizing pulse (Φ). Latch are connected between the data switch (B1, B2) and the correspondingly connected ones of the output switch (M1, M2) at said the lines (d, d ). The latch the potentials at the data lines (d, d ) immediately before the turn-off of the data line switch (B1, B2) and apply the latched potentials to the control terminals of the output switch (M1, M2). The data output control circuit for a semiconductor storage device has the above-described configurations. In the case where the output buffer is CMOS, one of the data lines (d, d) is brached into first and second branch lines (d1, d2). The first and second branch lines (d1, d2) are connected to the control terminals of the output switches (M1A, M2A) via switches (B1, B2) and data latches (F1, F2), respectively.
Inventors
- 👤 Masami Masuda
- 👤 Kenichi Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 20:10
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/1006; G11C7/1048; G11C7/106
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
285 words
A data output control circuit for a semiconductor storage device comprising: equalizing means connected between first and second data lines (d, d ) for setting said first and second data lines (d, d ) at a predetermined equal potential by making said first and second data lines (d, d ) conductive with respect to each other by applying an equalizing pulse (Φ) to a control terminal, data corresponding to data stored in a memory cell (MS) selected according to an address being outputted to said first and second data lines (d, d ); output buffer switching means having first and second output switching means (M1, M2) connected in series between a power source supply terminal and ground, an interconnection node (N1) between said output switching means (M1, M2) being a data output terminal, and one and the other of said pair of data lines (d, d ) being connected to one and the other of the control nodes (N4, N5) of said first and second output switching means; data line switching means (B1, B2) connected between said equalizing means (M3) and said output buffer switching means at least one of said pair of data lines (d, d ), said data line switching means being turned on and off by said equalizing pulse (W); and latch means (F1, F2) connected between said data line switching means (B1, B2) and the correspondingly connected ones of said output switching means (M1, M2) at said data lines (d, d ) for latching the potentials at said data lines (d, d ) immediately before the turn-off of said data line switching means (B1, B2) and applying said latched potentials to the control terminals of said output switching means (M1, M2).
Claim 2
Dependent Claim
285 words
A data output control circuit for a semiconductor storage device comprising: equalizing means connected between first and second data lines (d, d ) for setting said first and second data lines (d, d ) at a predetermined equal potential by making said first and second data lines (d, d ) conductive with respect to each other by applying an equalizing pulse (Φ) to a control terminal, data corresponding to data stored in a memory cell (MS) selected according to an address being outputted to said first and second data lines (d, d ); output buffer switching means having first and second output switching means (M1, M2) connected in series between a power source supply terminal and ground, an interconnection node (N1) between said output switching means (M1, M2) being a data output terminal, and one and the other of said pair of data lines (d, d ) being connected to one and the other of the control nodes (N4, N5) of said first and second output switching means; data line switching means (B1, B2) connected between said equalizing means (M3) and said output buffer switching means at least one of said pair of data lines (d, d ), said data line switching means being turned on and off by said equalizing pulse (W); and latch means (F1, F2) connected between said data line switching means (B1, B2) and the correspondingly connected ones of said output switching means (M1, M2) at said data lines (d, d ) for latching the potentials at said data lines (d, d ) immediately before the turn-off of said data line switching means (B1, B2) and applying said latched potentials to the control terminals of said output switching means (M1, M2).
Claim 3
Dependent Claim
43 words
A data output control circuit according to claim 1, wherein said data line switching means (B1, B2) is provided only between one of said pair of data lines (d, d ) and the correspondingly connected one of said first and second switching means.
Claim 4
Dependent Claim
48 words
A data output control circuit according to claim 1, wherein said data line switching means (B1, B2) is provided between one and the other of said pair of data lines (d, d ) and the correspondingly connected one and the other of said first and second switching means.
Claim 5
Dependent Claim
70 words
A data output controls circuit according to claim 1, wherein there is provided a data line switch (T1, T2) between said data line of said pair of data lines (d, d ) connected with said data line switching means (B1, B2) and ground, said data line switch turning off when an output enable signal ( OE) takes an enable state ("L") and turning on when taking a disable state ("H").
Claim 6
Dependent Claim
50 words
A data output control circuit according to claim 1, wherein there is provided a latch means switch (CG1, CG2) between said data latch means (F1, F2) and correspondingly connected said data lines (d, d ), said latch means switch being turned on only when said equalizing pulse (Φ) is outputted.
Claim 7
Dependent Claim
115 words
A data output control circuit according to claim 1, wherein said data line switching means (B1, B2) is constructed of a serial circuit connected between said power source supply terminal and ground and made of a first p-channel transistor (T11, T21), second p-channel transistor (T12, T22), first n-channel transistor (T13, T23), and second n-channel transistor (T14, T24), one of said pair of data lines (d, d ) is connected to the gates of said second p-channel transistor and said first n-channel transistor, and one of said control nodes (N4, N5) of said pair of output switching means (M1, M2) is connected to the interconnection node between said second p-channel transistor and said first n-channel transistor.
Claim 8
Dependent Claim
25 words
A data output control circuit according to claim 1, wherein said data latch means (F1, F2) has a pair of inverters connected reversely in parallel.
Claim 9
Dependent Claim
94 words
A data output control circuit according to claim 2, wherein said data line of said pair of data lines (d, d ) without said data line switching means (B1, B2) being connected therewith is connected to one input terminal of a logical element (G1) for executing an NOR logical operation, the other input terminal of said logical element is applied with an output enable signal ( OE ), and the output terminal of said logical element is connected to one of said control nodes (N4, N5) of said pair of switching means (M1, M2).
Claim 10
Dependent Claim
54 words
A data output control circuit according to claim 1, wherein first and second potential setting switching means (M3A, M3B) are connected to said first and second data lines (d, d ) and said power source supply terminal, and the control terminals of said potential setting switching means are supplied with said equalizing pulse Φ.
Claim 11
Dependent Claim
34 words
A data output control circuit according to claim 1, wherein said equalizing pulse is outputted from address transition detector means (ATD) for detecting a change of said address for selecting said memory cell (MS).
Claim 12
Dependent Claim
21 words
A data output control circuit according to claim 1, wherein said first and second switching means (M1, M2) are n-channel transistors.
Claim 13
Dependent Claim
275 words
A data output control circuit for a semiconductor storage device comprising: equalizing means connected between first and second data lines (d, d ) for setting said first and second data lines (d, d ) at a predetermined equal potential by making said first and second data lines (d, d ) conductive with respect to each other by applying an equalizing pulse (Φ) to a control terminal, data corresponding to data stored in a memory cell (MS) selected according to an address being outputted to said first and second data lines (d, d ); output buffer switching means (OB) having first and second output switching means (M1A, M2A) connected in series between a power source supply terminal and ground, an interconnection node (N1) between said output switching means (M1A, M2A) being a data output terminal, and first and second branch lines (d1, d2) branched from one of side data lines (d, d ) being connected to one and the other of the control nodes (N4, N5) of said first and second output switching means; data line switching means (B1, B2) connected to said first and second branch lines (d1, d2), said data line switching means being turned on and off by said equalizing pulse (Φ); and latch means (F1, F2) connected between said data line switching means (B1, B2) and the correspondingly connected ones of said output switching means (M1, M2) at said branch lines (d1, d2) for latching the potentials at said brnach lines (d1, d2) immediately before the turn-off of said data line switching means (B1, B2) and applying said latched potentials to the control terminals of said output switching means (M1 A, M2A).
Claim 14
Dependent Claim
275 words
A data output control circuit for a semiconductor storage device comprising: equalizing means connected between first and second data lines (d, d ) for setting said first and second data lines (d, d ) at a predetermined equal potential by making said first and second data lines (d, d ) conductive with respect to each other by applying an equalizing pulse (Φ) to a control terminal, data corresponding to data stored in a memory cell (MS) selected according to an address being outputted to said first and second data lines (d, d ); output buffer switching means (OB) having first and second output switching means (M1A, M2A) connected in series between a power source supply terminal and ground, an interconnection node (N1) between said output switching means (M1A, M2A) being a data output terminal, and first and second branch lines (d1, d2) branched from one of side data lines (d, d ) being connected to one and the other of the control nodes (N4, N5) of said first and second output switching means; data line switching means (B1, B2) connected to said first and second branch lines (d1, d2), said data line switching means being turned on and off by said equalizing pulse (Φ); and latch means (F1, F2) connected between said data line switching means (B1, B2) and the correspondingly connected ones of said output switching means (M1, M2) at said branch lines (d1, d2) for latching the potentials at said brnach lines (d1, d2) immediately before the turn-off of said data line switching means (B1, B2) and applying said latched potentials to the control terminals of said output switching means (M1 A, M2A).
Claim 15
Dependent Claim
31 words
A data output control circuit according to claim 12, wherein said first and second switching means (M1A, M2A) are p-channel and n-channel transistors, respectively, and said output buffer means is CMOS.
Claim 16
Dependent Claim
114 words
A data output control circuit according to claim 12, wherein said data line switching means (B1, B2) is constructed of a serial circuit connected between said power source supply terminal and ground and made of a first p-channel transistor (T11, T21), second p-channel transistor (T12, T22), first n-channel transistor (T13, T23), and second n-channel transistor (T14, T24), one of said pair of branch lines (d1, d2) is connected to the gates of said second p-channel transistor and said first n-channel transistor, and one of said control nodes (N4, N5) of said pair of output switching means (M1. M2) is connected to the interconnection node between said second p-channel transistor and said first n-channel transistor.
Claim 17
Dependent Claim
54 words
A data output control circuit according to claim 12, wherein first and second potential setting switching means (M3A, M3B) are connected to said first and second data lines (d, d ) and said power source supply terminal, and the control terminals of said potential setting switching means are supplied with said equalizing pulse (Φ).
References Cited (Backward Citations)
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