A method and apparatus for performing automatic test pattern generation

Claim 2

In a method of performing automatic test pattern generation for a circuit including registers, said method comprises the steps of: when aborting the process of automatic test pattern generation for one or more faults, specifying one or more registers which allow detection of said fault by scanning said specified registers; setting a scan request count limit; counting a scan request count for each of said registers; updating the scan request count of said specified registers; and recognizing one or more registers the scan request count of which is greater than said scan re­quest count limit, as critical registers.

Claim 3

A method according to claim 1, wherein one or more registers the scan request count of which is greater than specified number are recognized as critical regis­ters.

Claim 4

A method according to claim 1, one or more registers the scan request count of which has specified percent­age of total fault number which is greater than speci­fied value are recognized as critical registers.

Claim 5

A method according to claim 1, wherein, when speci­fied number of faults have been processed, specified number of registers with higher scan request count are recognized as critical registers.

Claim 6

A method according to claim 1, wherein, when speci­fied percentage of faults to total faults have been processed, specified number of registers with higher scan request count are recognized as critical regis­ters.

Claim 7

A method according to claim 1, wherein, when speci­fied fault coverage is not been achieved when specified number of faults have been processed, specified number of registers with higher scan request count are recog­nized as critical registers.

Claim 8

A method according to claim 1, wherein, when speci­fied fault coverage is not been achieved when specified percentage of faults to total faults have been proc­essed, specified number of registers with higher scan request count are recognized as critical registers.

Claim 9

A method according to claim 1, wherein, when speci­fied number of faults have been processed, registers the scan request count of which is greater than speci­fied value are recognized as critical registers.

Claim 10

A method according to claim 1, wherein, when speci­fied percentage of faults to total faults have been processed, registers the scan request count of which is greater than specified value are recognized as critical registers.

Claim 11

A method according to claim 1, wherein, when speci­fied number of faults have been processed, registers the scan request count of which is greater than speci­fied percentage of the number of faults which have been processed are recognized as critical registers.

Claim 12

A method according to claim 1, wherein, when speci­fied percentage of faults to total faults have been processed, registers the scan request count of which is greater than specified percentage of the number of faults which have been processed are recognized as critical registers.

Claim 14

In a method of design for testability for a circuit including registers, said method comprises the steps of : when aborting the process of automatic test pattern generation for one or more faults, specifying one or more registers which allow detection of said fault by scanning said specified registers; setting a scan request count limit; counting a scan request count for each of said registers; updating the scan request count of said specified registers; recognizing one or more registers the scan request count of which is greater than said scan re­quest count limit, as critical registers; and at each time when one of said registers is recognized by said register recognition means, changing said recognized register to a scan register one after another, thereby reconstructing the circuit.

Claim 15

In a method of design for testability for a circuit including registers, said method comprises the steps of : when aborting the process of automatic test pattern generation for one or more faults, specifying one or more registers which allow detection of said fault by scanning said specified registers; setting a scan request count limit; counting a scan request count for each of said registers; updating the scan request count of said specified registers; recognizing one or more registers the scan request count of which is greater than said scan re­quest count limit, as critical registers; and at each time when one of said registers is recognized by said register recognition means, changing said recognized register to a scan register one after another, thereby reconstructing the circuit.

Claim 16

In an apparatus for performing automatic test pattern generation for a circuit including registers, said apparatus comprises: critical register recognition means for, when aborting the process of automatic test pattern genera­tion for one or more faults, specifying one or more registers which allow detection of said fault by scan­ning said specified registers; count set means for setting a scan request count limit; count means for counting a scan request count for each of said registers; count update means for updating the scan request count of said specified registers; and register recognition means for recognizing one or more registers the scan request count of which is greater than said scan request count limit, as critical registers.

Claim 17

In an apparatus for performing automatic test pattern generation for a circuit including registers, said apparatus comprises: critical register recognition means for, when aborting the process of automatic test pattern genera­tion for one or more faults, specifying one or more registers which allow detection of said fault by scan­ning said specified registers; count set means for setting a scan request count limit; count means for counting a scan request count for each of said registers; count update means for updating the scan request count of said specified registers; and register recognition means for recognizing one or more registers the scan request count of which is greater than said scan request count limit, as critical registers.

Claim 18

An apparatus according to claim 14, wherein said register recognition means recognizes one or more registers the scan request count of which is greater than specified number, as critical registers.

Claim 19

An apparatus according to claim 14, wherein said register recognition means recognizes one or more registers the scan request count of which has a per­centage of total fault number which is greater than specified value, as critical registers.

Claim 20

An apparatus according to claim 14, wherein, when specified number of faults have been processed, said register recognition means recognizes specified number of registers with higher scan request count, as criti­cal registers.

Claim 21

An apparatus according to claim 14, wherein, when specified percentage of faults to total faults have been processed, said register recognition means recog­nizes specified number of registers with higher scan request count, as critical registers.

Claim 22

An apparatus according to claim 14, wherein, when specified fault coverage is not been achieved when specified number of faults have been processed, said register recognition means recognizes specified number of registers with higher scan request count, as criti­cal registers.

Claim 23

An apparatus according to claim 14, wherein, when specified fault coverage is not been achieved when specified percentage of faults to total faults have been processed, said register recognition means recog­nizes specified number of registers with higher scan request count, as critical registers.

Claim 24

An apparatus according to claim 14, wherein, when specified number of faults have been processed, said register recognition means recognizes registers the scan request count of which is greater than specified value, as critical registers.

Claim 25

An apparatus according to claim 14, wherein, when specified percentage of faults to total faults have been processed, said register recognition means recog­nizes registers the scan request count of which is greater than specified value, as critical registers.

Claim 26

An apparatus according to claim 14, wherein, when specified number of faults have been processed, said register recognition means recognizes registers the scan request count of which is greater than specified percentage of the number of faults which have been processed, as critical registers.

Claim 27

An apparatus according to claim 14, wherein, when specified percentage of faults to total faults have been processed, said register recognition means recog­nizes registers the scan request count of which is greater than specified percentage of the number of faults which have been processed, as critical regis­ters.

Claim 29

In an apparatus for design for testability for a circuit including registers, said apparatus comprises: critical register recognition means for, when aborting the process of automatic test pattern genera­tion for one or more faults, specifying one or more registers which allow detection of said fault by scan­ning said specified registers; count set means for setting a scan request count limit; count means for counting a scan request for each of said registers; count update ineans for updating the scan request count of said specified registers; register recognition means for recognizing one or more registers the scan request count of which is greater than said scan request count limit, as critical registers; and circuit reconstruction means for, at each time when one of said registers is recognized by said register recognition means, changing said recognized register to a scan register one after another, thereby reconstructing the circuit.

Claim 30

In an apparatus for design for testability for a circuit including registers, said apparatus comprises: critical register recognition means for, when aborting the process of automatic test pattern genera­tion for one or more faults, specifying one or more registers which allow detection of said fault by scan­ning said specified registers; count set means for setting a scan request count limit; count means for counting a scan request for each of said registers; count update ineans for updating the scan request count of said specified registers; register recognition means for recognizing one or more registers the scan request count of which is greater than said scan request count limit, as critical registers; and circuit reconstruction means for, at each time when one of said registers is recognized by said register recognition means, changing said recognized register to a scan register one after another, thereby reconstructing the circuit.