A programmable semiconductor memory apparatus

Claim 2

A programmable semiconductor memory apparatus compris­ing: a memory cell array (1, 2, 3); a plurality of bit lines (B₁, B₂,...) connected to said memory cell array; a bus line (B u1 , B u2 ,...) connected to one of said bit lines in response to an address signal; a data sense circuit (4) connected to said bus line for reading data from said memory cell array, and a means (Q 1D , Q 2D ,...) for storing an identifying code for identifying said programmable semiconductor memory apparatus, said storing means being coupled to said bus line, thereby enabling said identifying code to be read externally.

Claim 3

The semiconductor memory device according to claim 1, wherein said means (Q 1D ,...) for storing the identifying code is connected to said bus line (B u1 ,...) between said bus line (B u1 ,...) and said data sense circuit (4).

Claim 4

The semiconductor memory apparatus according to claim 1 or 2, wherein a spare bit line (B s1 ,...) is connected to said bus line so that one of said plurality of bit lines which is faulty is replaced by a bit line.

Claim 5

The programmable semiconductor memory apparatus according to anyone of claims 1 to 3, wherein all word lines (W₁, W₂,...) of said memory cell array (1, 2, 3) are made non-active when the identifying code is read out.

Claim 6

The programmable semiconductor memory apparatus according to anyone of claims 1 to 4, wherein said means for storing the identifying code comprises a first and second transistor each connected to said bus line, the first transistor having a first threshold voltage and the second transistor having a second threshold voltage, and when a gate voltage is applied to said first and second transistors, the first transistor becomes conductive and the second transistor becomes non-conductlve, thereby providing logic "1" and "0", respectively.

Claim 7

The programmable semiconductor memory apparatus according to anyone of claims 1 to 4, wherein said means for storing the identifying code comprises a transistor (Q 1E , Q 2E ,...) for determining logic "1" and logic "0" depending on whether or not the drain of the transistor is connected to the bus line through a fuse (S 1E , S 2E ,...) provided between the drain and the bus line.

Claim 8

The programmable semiconductor memory apparatus according to anyone of claims 1 to 6, wherein said means for storing the identifying code is provided within said data sense circuit (4).

Claim 9

The programmable semiconductor memory apparatus according to anyone of claims 1 to 6, wherein said means for storing the identifying code is provided within the output buffer circuit.

Claim 10

A programmable semiconductor memory apparatus compris­ing: a memory cell array (1, 2, 3); a plurality of bit lines (B₁, B₂,...) connected to said memory cell array; a bus line (B u1 , B u2 ,...) connected to one of said bit lines in response to an address signal; a data sense circuit (4) connected to said bus line for reading data from said memory cell array, and a means for storing an identifying code for identifying said programmable semiconductor memory apparatus, said storing means being coupled to said bus line, thereby enabling said identifying code to be read externally, and a switch means, connected to said data sense circuit, for receiving a signature signal designating that the identifying code has been read out from said memory cell array and for producing the identifying code regard­less of the output of the data sense circuit.

Claim 11

A programmable semiconductor memory apparatus compris­ing: a memory cell array (1, 2, 3); a plurality of bit lines (B₁, B₂,...) connected to said memory cell array; a bus line (B u1 , B u2 ,...) connected to one of said bit lines in response to an address signal; a data sense circuit (4) connected to said bus line for reading data from said memory cell array, and a means for storing an identifying code for identifying said programmable semiconductor memory apparatus, said storing means being coupled to said bus line, thereby enabling said identifying code to be read externally, and a switch means, connected to said data sense circuit, for receiving a signature signal designating that the identifying code has been read out from said memory cell array and for producing the identifying code regard­less of the output of the data sense circuit.

Claim 12

The programmable semiconductor memory apparatus according to claim 9, wherein said switching means controls a gate of a pull-up transistor to determine whether a data from said data sense circuit is output or the said identifying code is output.

Claim 13

A programmable semiconductor memory device comprising: a spare memory cell array block; a data sense circuit for reading data from said memory cell array block, a bus line connected to the output of both said memory cell array block and said spare memory cell array block; a means for storing an identifying code for identifying said programmable semiconductor memory device, said storing means being coupled to said bus line, thereby enabling said identifying code to be read externally and a switching means provided between said memory cell array block and said bus line and between said spare memory cell array block and the bus line wherein, when said memory cell array block is faulty, the spare memory cell array block is connected to said bus line.

Claim 14

A programmable semiconductor memory device comprising: a spare memory cell array block; a data sense circuit for reading data from said memory cell array block, a bus line connected to the output of both said memory cell array block and said spare memory cell array block; a means for storing an identifying code for identifying said programmable semiconductor memory device, said storing means being coupled to said bus line, thereby enabling said identifying code to be read externally and a switching means provided between said memory cell array block and said bus line and between said spare memory cell array block and the bus line wherein, when said memory cell array block is faulty, the spare memory cell array block is connected to said bus line.

Claim 15

The programmable semiconductor memory device according to claim 11, wherein said memory cell array block comprises a single bit line.

Claim 16

The semiconductor memory device according to claim 11 or 12, wherein said means for storing the identifying code is provided between said bus line and said data sense circuit.

Claim 17

The semiconductor memory device according to anyone of claims 11 to 13, wherein a spare bit line is connected to said bus line so that one of said plurality of bit lines which is faulty is replaced by said spare bit line.

Claim 18

The programmable semiconductor memory device according to anyone of claims 11 to 14, wherein all word lines of said memory cell array block are made non-active when the identifying code is read out.

Claim 19

The programmable semiconductor memory device according to anyone of claims 11 to 15, wherein said means for storing the identifying code comprises first and second transistors each connected to said bus line, the first transistor having a first threshold voltage and the second transistor having a second threshold voltage, and when a gate voltage is applied to said first and second transistors, the first transistor becomes conductive and the second transistor becomes non-conductive, thereby providing logic "1" and "0", respectively.

Claim 20

The programmable semiconductor memory device according to anyone of claims 11 to 15, wherein said means for storing the identifying code comprises a transistor for determining logic "1" and logic "0" depending on whether or not the drain of the transistor is connected to the bus line through a fuse provided between the drain and the bus line.