EP0404559A2
Expired / Lapsed
EP
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Multiprocessor system with multiple instruction sources
Assignee: Sun Microsystems Inc
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Filing: 1990-06-21
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Granted: —
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Expires: 2010-06-21
Abstract
Abstract Digital processing apparatus comprising a set of interconnected processing units (58, 60, 82, 84) for normally processing an instruction stream (86), at least one of the processing units (60) including insert means for inserting one or more inserted-instructions to be processed by the first processing element in the same manner as, and without affecting processing sequence of, the instructions from the first instruction source.
Inventors
- 👤 Steven Frank
- 👤 Henry Burkhardt, Iii
- 👤 Frederick D. Weber
- 👤 Linda Q. Lee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 15:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3865; G06F11/00; G06F11/004; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0724; G06F11/073; G06F11/0793; G06F9/30003; G06F9/30007; G06F9/30032; G06F9/3004; G06F9/30043; G06F9/3005; G06F9/30072; G06F9/3824; G06F9/3826; G06F9/3828; G06F9/383; G06F9/3836; G06F9/3851; G06F9/3854; G06F9/3858; G06F9/38585; G06F9/3877; G06F9/3885
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
75 words
Digital processing apparatus comprising a set of interconnected processing elements, said set of processing elements including a first processing element for normally processing an instruction stream including instructions from a first instruction source, at least one of said processing elements including insert means for inserting one or more inserted-instructions to be processed by the first processing element in the same manner as, and without affecting processing sequence of, the instructions from the first instruction source.
Claim 2
Dependent Claim
75 words
Digital processing apparatus comprising a set of interconnected processing elements, said set of processing elements including a first processing element for normally processing an instruction stream including instructions from a first instruction source, at least one of said processing elements including insert means for inserting one or more inserted-instructions to be processed by the first processing element in the same manner as, and without affecting processing sequence of, the instructions from the first instruction source.
Claim 3
Dependent Claim
40 words
Apparatus according to claim 1, further comprising instruction pipeline means for interconnecting said processing elements and for carrying said instructions, and wherein said insert means includes means for inserting one or more of said inserted-instructions into said instruction pipeline means.
Claim 4
Dependent Claim
20 words
Apparatus according to claim 1, wherein said inserted-instructions have the same format as the instructions from the first instruction source.
Claim 5
Dependent Claim
31 words
Apparatus according to claim 3, wherein said format includes a selected number of digital instruction bits, wherein at least a first set of said instruction bits form a first instruction field.
Claim 6
Dependent Claim
34 words
Apparatus according to claim 3, wherein said format includes a first set of digital instruction bits for specifying selected address signals, and a second set of digital instruction bits for specifying selected command signals.
Claim 7
Dependent Claim
14 words
Apparatus according to claim 1, wherein said first instruction source includes a memory element.
Claim 8
Dependent Claim
21 words
Apparatus according to claim 6, wherein said memory element includes an instruction cache element for storing digital values representative of instructions.
Claim 9
Dependent Claim
41 words
Apparatus according to claim 7, wherein said first processing element includes an execution unit (CEU), said CEU including means for asserting signals to said instruction cache element to cause instructions to be transmitted from said instruction cache element to said CEU.
Claim 10
Dependent Claim
18 words
Apparatus according to claim 7, wherein said instructions include cache management instructions inserted by said instruction cache element.
Claim 11
Dependent Claim
19 words
Apparatus according to claim 7, wherein said instruction cache element includes means for storing instructions representative of program steps.
Claim 12
Dependent Claim
79 words
Apparatus as claimed in claim 1, in which said set of processing elements further including input/output processing means for processing signals received from, and transmitted to, a peripheral device, said input/output processing means including DMA insert means for responding to selected signals from a peripheral device to insert direct memory access (DMA) instructions to be processed by the first processing element in the same manner as, and without affecting processing sequence of, the instructions from the first instruction source.
Claim 13
Dependent Claim
27 words
Apparatus according to claim 11, wherein said input/output processing means includes a peripheral interface unit (XIU) for controlling signals received from, and transmitted by, a peripheral device.
Claim 14
Dependent Claim
22 words
Apparatus according to claim 11, wherein said input/output processing means includes graphics controller means for controlling signals transmitted to a display device.
Claim 15
Dependent Claim
21 words
Apparatus according to claim 11, wherein said input/output processing means includes text searching means for searching data structures representative of text.
Claim 16
Dependent Claim
62 words
Apparatus according to claim 1 or 11, wherein at least a selected one of said processing elements includes at least a first associated register element for storing digital values representative of data, and said insert means includes means for inserting instructions to control movement of data into and out of selected register elements associated with said at least one selected processing element.
Claim 17
Dependent Claim
66 words
Apparatus according to claim 1 or 11, wherein at least a selected one of said processing elements includes at least a first associated register element for storing digital values representative of data, and said insert means includes means for inserting instructions to cause executing of selected logical operations on selected digital values stored in selected register elements associated with said at least one selected processing element.
Claim 18
Dependent Claim
57 words
Apparatus according to claim 1 or 11, wherein at least one of said processing elements includes trap means, responsive to a trap signal, for initiating a trap sequence, said trap sequence including selected program steps to be executed in response to a trap signal, and said insert-means includes means for inserting instructions for generating a trap signal.
Claim 19
Dependent Claim
59 words
Apparatus according to claim 1, 11 or 17, wherein at least one of said processing elements includes interrupt means, responsive to an interrupt signal, for initiating an interrupt sequence, said interrupt sequence including selected program steps to be executed in response to an interrupt signal, and said insert means includes means for inserting instructions for initiating an interrupt sequence.
Claim 20
Dependent Claim
22 words
Apparatus according to claim 18, wherein said interrupt means includes means for generating a trap signal in response to an interrupt signal.
Claim 21
Dependent Claim
77 words
A digital processing method comprising the steps of interconnecting a set of processing elements, configuring at least a first processing element to normally process an instruction stream including instructions from a first instruction source, and configuring at least a second one of said processing elements to insert one or more inserted-instructions to be processed by the first processing element in the same manner as, and without affecting processing sequence of, the instructions from the first instruction source.
Claim 22
Dependent Claim
77 words
A digital processing method comprising the steps of interconnecting a set of processing elements, configuring at least a first processing element to normally process an instruction stream including instructions from a first instruction source, and configuring at least a second one of said processing elements to insert one or more inserted-instructions to be processed by the first processing element in the same manner as, and without affecting processing sequence of, the instructions from the first instruction source.
References Cited (Backward Citations)
No citation records indexed.
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