EP0404413A2
Expired / Lapsed
EP
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Microprocessor hold and lock circuitry
Assignee: International Business Machines Corp
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Filing: 1990-06-11
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Granted: —
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Expires: 2010-06-11
Abstract
Abstract A logic circuit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.
Inventors
- 👤 Ralph Murray Begun
- 👤 Patrick Maurice Bland
- 👤 Mark Edward Dean
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 16:41
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/285; G06F13/36; G06F13/362
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
93 words
A computer system comprising: a microprocessor (102) having means responsive to an active state on a control port for releasing the microprocessor (102) from controlling a first bus coupled between the microprocessor (102) and a first buffer (106); characterised in that the control port is coupled with a hold output port of a logic circuit (126,138) comprising bus locking means (138) for holding the hold output port in an inactive state for a predetermined time period in response to a change in logic state on a hold request port from active to inactive.
Claim 2
Dependent Claim
93 words
A computer system comprising: a microprocessor (102) having means responsive to an active state on a control port for releasing the microprocessor (102) from controlling a first bus coupled between the microprocessor (102) and a first buffer (106); characterised in that the control port is coupled with a hold output port of a logic circuit (126,138) comprising bus locking means (138) for holding the hold output port in an inactive state for a predetermined time period in response to a change in logic state on a hold request port from active to inactive.
Claim 3
Dependent Claim
100 words
A computer system as claimed in claim 1 wherein the bus locking means comprises a counter having a clock input coupled to a system clock, a time output on which an active state is asserted at the expiry of the predetermined time period for permitting the hold output port to assert an active state after the predetermined time period expires, and means for clearing the counter in response to an inactive state on a reset input, wherein the logic circuit is operable for preventing the hold output port from asserting an active state when the reset input is asserted active.
Claim 4
Dependent Claim
22 words
A computer system as claimed in claim 1 or claim 2 wherein the logic circuit comprises a Programmable Array Logic (PAL) circuit.
Claim 5
Dependent Claim
125 words
A computer system as claimed in claim 3 further comprising: a system bus coupled between the first buffer and a second buffer; a bus control circuit coupled to the system bus; a third buffer coupled between the system bus and an Input/Output (I/O) bus; at least one planar I/O device coupled to the I/O bus; a fourth bus coupled to the second buffer; a plurality of sockets coupled to the fourth bus for receiving peripheral device adapter cards; a direct memory access controller coupled to the system bus; a memory coupled to the system bus; and a central arbitration control point coupled between the fourth bus and the bus control circuit for asserting a logic state on the hold request port of the PAL circuit.
Claim 6
Dependent Claim
53 words
A computer system as claimed in claim 4 wherein the PAL circuit is coupled between the first bus, at least one planar I/O device, the bus control circuit, and the central arbitration control point, and is responsive to logic signal therefrom for asserting a logic state on the control port of the microprocessor.
Claim 7
Dependent Claim
89 words
A computer system as claimed in claim 2 wherein the logic circuit is operable to assert an active state on the reset input in response to, and immediately after assertion of an inactive state on the hold request port, whereupon the logic circuit is operable to assert an inactive state on the reset input in response to either assertion of an active state on the output of the counter, or an idle signal for indicating that the microprocessor has been idle for a predetermined plurality of consecutive clock cycles.
Claim 8
Dependent Claim
26 words
A computer system as claimed in claim 6 wherein the idle signal is generated in response to the microprocessor being idle for two consecutive clock cycles.
Claim 9
Dependent Claim
16 words
A computer system as claimed in any preceding claim wherein the microprocessor is an 80486 microprocessor.
Claim 10
Dependent Claim
15 words
A computer system as claimed in any preceding claim wherein the the counter is 74F393
Claim 11
Dependent Claim
62 words
A logic circuit, for use with a microprocessor, the logic circuit comprising in combination: a hold output port; and a hold request input port; and bus locking means for holding the output port inactive for a predetermined period of time in response to a change in the logic stat of the hold request port from an active state to an inactive state.
Claim 12
Dependent Claim
62 words
A logic circuit, for use with a microprocessor, the logic circuit comprising in combination: a hold output port; and a hold request input port; and bus locking means for holding the output port inactive for a predetermined period of time in response to a change in the logic stat of the hold request port from an active state to an inactive state.
References Cited (Backward Citations)
No citation records indexed.
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