EP0404078A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Communication apparatus for reassembling packets received from a network into a message
Assignee: Hitachi Microcomputer System Ltd
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Filing: 1990-06-19
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Granted: —
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Expires: 2010-06-19
Abstract
Abstract In a network having a plurality of node apparatuses (200A-200F) connected to a transmission line (100), each node apparatus segmenting a transmission message into information blocks of a predetermined length and transmitting time to the transmission line (100) in the form of a fixed length packet (cell) having a source address, each node apparatus sequentially stores packets having different source addresses in vacant memory blocks of a buffer memory . There is written in each memory block the packet data as well as a next address pointer indicating a memory block in which the next received packet having the same source address is stored. When a packet containing the last information block of a message is received, stored in a read address queue is the address indicating the memory block which stores the first information block of the same packet. Reading the first block of a message from the buffer memory is executed in accordance with an address read from the read address queue, and reading the following blocks is executed in accordance with the next address pointer. Read/write of the buffer memory is alternately executed in units of memory blocks.
Inventors
- 👤 Yoshihiro Takiyasu
- 👤 Mitsuhiro Yamaga
- 👤 Kazunori Nakamura
- 👤 Eiichi Amada
- 👤 Hidehiko Jusa
- 👤 Naoya Kobayashi
- 👤 Osamu Takada
- 👤 Satoru Hirayama
- 👤 Tatsuhito Iiyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 20:03
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L49/00; H04L49/30; H04L49/3009; H04L49/25; H04L49/252
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
482 words
A communication apparatus for receiving a plurality of fixed length packets transmitted from a plurality of transmission source apparatuses (200A-200B) and reassembling a communication message from a plurality of packets having the same transmission source address, each packet having a header field (14) including a transmission source address and a message information field (16) including an information block obtained by segmenting a message, comprising: a buffer memory (66) divided into a plurality of memory blocks (66-i) for storing packet data; first memory means (83) for storing addresses each indicating a vacant memory block (66-i) within said buffer memory; second memory means (80) for storing next address pointers correspondingly with each transmission source address, each next address pointer indicating a memory block (66-i) in which the data of a packet to be received next are stored; third memory means (81) for storing addresses correspondingly with each transmission source address, each address indicating a memory block (66-i) in which the packet data including the first information block of a message are stored; fourth memory means (84) for storing addresses correspondingly with each transmission source address, each address indicating a memory block (66-i) stored in which are the packet data including the first information block of a message allowed to be reassembled; write control means (70) which operates such that when there is received a packet including the first information block of a message transmitted upon segmentation into a plurality of information blocks, an address read from said first memory means (83) is stored in said third memory means (81), the data of said received packet are stored in a vacant memory block (66-i) indicated by said address, and another address read from said first memory means (83) is stored in said second memory means (80) and in said memory block (66-i) storing said packet data; and that when there is received a packet including one of the second and following information blocks of said message, the data of said received packet are stored in a memory block (66-i) indicated by an address read from said second memory means (80), if said received packet does not include the last information block of said message, an address read from said first memory means (83) is stored in said second memory means (80) and in said memory block (66-i) storing the data of said received packet, and if said received packet includes the last information block of said message, an address read from said third memory means (81) is stored in said fourth memory means (84); and read control means (71, 73) which operates such that the first information block of a message is read from the memory block (66-i) indicated by an address read from said fourth memory means (84), and the second and following information blocks of said message are sequentially read in accordance with next address pointers (6615) read from respective memory blocks (66-i).
Claim 2
Dependent Claim
482 words
A communication apparatus for receiving a plurality of fixed length packets transmitted from a plurality of transmission source apparatuses (200A-200B) and reassembling a communication message from a plurality of packets having the same transmission source address, each packet having a header field (14) including a transmission source address and a message information field (16) including an information block obtained by segmenting a message, comprising: a buffer memory (66) divided into a plurality of memory blocks (66-i) for storing packet data; first memory means (83) for storing addresses each indicating a vacant memory block (66-i) within said buffer memory; second memory means (80) for storing next address pointers correspondingly with each transmission source address, each next address pointer indicating a memory block (66-i) in which the data of a packet to be received next are stored; third memory means (81) for storing addresses correspondingly with each transmission source address, each address indicating a memory block (66-i) in which the packet data including the first information block of a message are stored; fourth memory means (84) for storing addresses correspondingly with each transmission source address, each address indicating a memory block (66-i) stored in which are the packet data including the first information block of a message allowed to be reassembled; write control means (70) which operates such that when there is received a packet including the first information block of a message transmitted upon segmentation into a plurality of information blocks, an address read from said first memory means (83) is stored in said third memory means (81), the data of said received packet are stored in a vacant memory block (66-i) indicated by said address, and another address read from said first memory means (83) is stored in said second memory means (80) and in said memory block (66-i) storing said packet data; and that when there is received a packet including one of the second and following information blocks of said message, the data of said received packet are stored in a memory block (66-i) indicated by an address read from said second memory means (80), if said received packet does not include the last information block of said message, an address read from said first memory means (83) is stored in said second memory means (80) and in said memory block (66-i) storing the data of said received packet, and if said received packet includes the last information block of said message, an address read from said third memory means (81) is stored in said fourth memory means (84); and read control means (71, 73) which operates such that the first information block of a message is read from the memory block (66-i) indicated by an address read from said fourth memory means (84), and the second and following information blocks of said message are sequentially read in accordance with next address pointers (6615) read from respective memory blocks (66-i).
Claim 3
Dependent Claim
42 words
A communication apparatus according to claim 1, wherein said write and read control means (70, 71, 73) alternately access said buffer memory at a predetermined operation cycle, and the packet data of one memory block (66-i) are processed at each operation cycle.
Claim 4
Dependent Claim
46 words
A communication apparatus according to claim 1, further comprising means for extracting said message information field (16) from each received packet, whereby the contents of said message information field (16) are stored as said packet data in each memory block (66-i) of said buffer memory (66).
Claim 5
Dependent Claim
66 words
A communication apparatus according to claim 1, wherein said write control means (70) includes means for storing, when a received packet includes all information of a message, an address read from said first memory means (83) directly, or via said third memory (81), in said fourth memory means (84), and storing the data of said received packet in a memory block (66-i) indicated by said address.
Claim 6
Dependent Claim
447 words
A communication apparatus for receiving a plurality of fixed length packets transmitted from a plurality of transmission source apparatuses, and reassembling a communication message from a plurality of packets having the same transmission source address, each packet having a header field (14) including a transmission source address, a message information field (16) including an information block obtained by segmenting a message and a code field (15) for indicating the position of an information block within a message, comprising: a buffer memory (66) divided into a plurality of memory blocks (66-i) for storing packet data; first memory means (83) for storing addresses each indicating a vacant memory block (66-i) within said buffer memory; second memory means (80) for storing addresses correspondingly with each transmission source address, each address indicating a memory block (66-i) storing the data of a preceding packet; third memory means (81) for storing addresses correspondingly with each transmission source address, each address indicating a memory block (66-i) in which the packet data including the first information block of a message are stored; fourth memory means (84) for storing addresses correspondingly with each transmission source address, each address indicating a memory block (66-i) stored in which are the packet data including the first information block of a message allowed to be reassembled; write control means (70) which operates such that when there is received a packet including the first information block of a message transmitted upon segmentation into a plurality of information blocks, an address read from said first memory means (83) is stored in said third memory means (81), and the data of said received packet are stored in a vacant memory block (66-i) indicated by said address; and that when there is received a packet including one of the second and following information blocks of said message, the data of said received packet are stored in a memory block (66-i) indicated by an address read from said second memory means (80), and said address is stored as a next address pointer (6615) in a memory block (66-i) at a predetermined memory area indicated by an address read from said second means (80), said message, and if said received packet includes the last information block of said message, an address read from said third memory means (81) is stored in said fourth memory means (84); and read control means (71, 73) which operates such that the first information block of a message is read from the memory block (66-i) indicated by an address read from said fourth memory means (84), and the second and following information blocks of said message are sequentially read in accordance with next address pointers (6615) read from respective memory blocks.
Claim 7
Dependent Claim
447 words
A communication apparatus for receiving a plurality of fixed length packets transmitted from a plurality of transmission source apparatuses, and reassembling a communication message from a plurality of packets having the same transmission source address, each packet having a header field (14) including a transmission source address, a message information field (16) including an information block obtained by segmenting a message and a code field (15) for indicating the position of an information block within a message, comprising: a buffer memory (66) divided into a plurality of memory blocks (66-i) for storing packet data; first memory means (83) for storing addresses each indicating a vacant memory block (66-i) within said buffer memory; second memory means (80) for storing addresses correspondingly with each transmission source address, each address indicating a memory block (66-i) storing the data of a preceding packet; third memory means (81) for storing addresses correspondingly with each transmission source address, each address indicating a memory block (66-i) in which the packet data including the first information block of a message are stored; fourth memory means (84) for storing addresses correspondingly with each transmission source address, each address indicating a memory block (66-i) stored in which are the packet data including the first information block of a message allowed to be reassembled; write control means (70) which operates such that when there is received a packet including the first information block of a message transmitted upon segmentation into a plurality of information blocks, an address read from said first memory means (83) is stored in said third memory means (81), and the data of said received packet are stored in a vacant memory block (66-i) indicated by said address; and that when there is received a packet including one of the second and following information blocks of said message, the data of said received packet are stored in a memory block (66-i) indicated by an address read from said second memory means (80), and said address is stored as a next address pointer (6615) in a memory block (66-i) at a predetermined memory area indicated by an address read from said second means (80), said message, and if said received packet includes the last information block of said message, an address read from said third memory means (81) is stored in said fourth memory means (84); and read control means (71, 73) which operates such that the first information block of a message is read from the memory block (66-i) indicated by an address read from said fourth memory means (84), and the second and following information blocks of said message are sequentially read in accordance with next address pointers (6615) read from respective memory blocks.
Claim 8
Dependent Claim
103 words
A communication apparatus according to claim 5, wherein said write control means includes means (98) for adding a constant value to an address read from said first memory means (83), whereby when there is received a packet including the first information block of a message, an address outputted from said adding means (98) is stored in said second memory (80), and when there is received one of the second and following information blocks of said message, said address as a next address pointer is stored in said buffer memory at the location indicated by an address read from said second memory means (80).
Claim 9
Dependent Claim
42 words
A communication apparatus according to claim 5, wherein said write and read control menas (70, 71, 73) alternately access said buffer memory at a predetermined operation cycle, and the packet data of one memory block (66-i) are processed at each operation cycle.
Claim 10
Dependent Claim
59 words
A communication apparatus according to claim 5, wherein each memory block (66-i) stores at least the contents of said message information field (16) and position code field included in a received packet, and said read control means (71, 73) discriminates the last information block of a message in accordance with said position code read from each memory block (66-i).
References Cited (Backward Citations)
No citation records indexed.
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