EP0401588A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
VME-Multibus II interface adapter
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1990-05-21
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Granted: —
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Expires: 2010-05-21
Abstract
Abstract Interface adapter VME bus - MULTIBUS II (PSB bus) consisting in a printed circuit artwork comprising logical circuits for converting VME interface signals in PSB interface signals and viceversa, provided with connectors for connection to a standard VME board on one edge and to a PSB bus on the opposite edge and having a size such that when coupled to a VME standard board the size of the two coupled boards is equal to the size of a standard PSB board and can be inserted in a housing sized for a standard PSB.
Inventors
- 👤 Roberto Boioli
- 👤 Carlo Munero
- 👤 Lucio Savogin
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 21:16
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/4063; G06F13/409
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
153 words
1) Interface adapter from VME to PSB consisting in a printed circuit artwork comprising logical circuits for converting interface signals conforming to the VME bus protocol in interface signals conforming to the PSB bus protocol and viceversa, said artwork being provided with first connection means on a first edge of said artwork for connection to a board forming an electronic unit with a VME interface, and with second connection means, on a second edge of said artwork, opposite to said first edge, for connection to a PSB bus, said interface adapter artwork having a size such that when said artwork is coupled to said board forming an electronic unit with VME interface, the pair of said coupled boards has a size equal to the one of a standard PSB board for connection to a PSB bus, so that said pair can be inserted in a housing sized to contain a standard PSB board.
Claim 2
Dependent Claim
153 words
1) Interface adapter from VME to PSB consisting in a printed circuit artwork comprising logical circuits for converting interface signals conforming to the VME bus protocol in interface signals conforming to the PSB bus protocol and viceversa, said artwork being provided with first connection means on a first edge of said artwork for connection to a board forming an electronic unit with a VME interface, and with second connection means, on a second edge of said artwork, opposite to said first edge, for connection to a PSB bus, said interface adapter artwork having a size such that when said artwork is coupled to said board forming an electronic unit with VME interface, the pair of said coupled boards has a size equal to the one of a standard PSB board for connection to a PSB bus, so that said pair can be inserted in a housing sized to contain a standard PSB board.
Claim 3
Dependent Claim
99 words
2) Interface adapter as claimed in Claim 1, comprising first logic means (20) for watching the state of a PSB bus connected to said second connection means and second logic means (21) for converting access request to a VME interface and interrupt requests, received through said first connection means and generated by an electronic unit with VME interface connected to said first connection means, in signals (BREQ,ARBi) on said second connection means, said signals conforming to an arbitration and acquisition protocol of a PSB bus, and for generating a signal (RESWIN) indicating that the PSB bus has been acquired.
Claim 4
Dependent Claim
101 words
3) Interface adapter as claimed in claim 2, comprising third logic means (22,26,27) activated by said signal of PSB bus acquired, joint with an interrupt signal received through said first means and generated by an electronic unit connected to said first connection means, for requesting and obtaining from said electronic unit an interrupt vector and for transferring through said second connection means, to a PSB bus connected to said second connection means, a code identifying an interrupting unit and a destination unit and said interrupt vector, and for generating a signal of message absence (NOMESS) when said third means are inactive.
Claim 5
Dependent Claim
102 words
4) Interface adapter as claimed in Claim 3, comprising fourth logic means (23), activated by said signal of PSB bus acquired, joint with a request signal received through said first means and generated by an electronic unit connected to said first connection means, for receiving from said electronic unit a destination address and data to be written and for transferring, through said second connection means, to a PSB bus connected to said second connection means, at subsequent times, said destination address and said data to be written and for generating a signal of access absence (NACS) when said fourth means are inactive.
Claim 6
Dependent Claim
98 words
5) Interface adapter as claimed in Claim 4, comprising fifth logic means, (24) for detecting accesses to said PSB bus, which accesses have not been activated by said third and fourth logic means, for transferring to said electronic unit operation requests on said PSB bus, concurrent with said accesses and for asserting a second performed operation signal (SC4) on said PSB bus, on receipt of a first performed operation signal (DTACK) from said electronic unit, said fifth means being set in a wait state (WREQ) on detection of an end of transfer signal (SC3) on said PSB bus.
References Cited (Backward Citations)
No citation records indexed.
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