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EP0399662A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Procedure for annealing of semiconductors

Assignee: AT&T Inc
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Filing: 1990-04-25
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Granted: —
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Expires: 2010-04-25
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Abstract

Abstract This invention is directed to the fabrication of semiconductor devices, especially those comprising III-V and II-VI compound semiconductor materials, and involves annealing, especially Rapid Thermal Annealing (RTA), of semiconductor wafers, especially those implanted with a dopant(s). The invention is also concerned with a black-box implement used in combination with the RTA. The process includes enclosing a wafer (1) to be annealed within a "black-box" comprising components (10,11,12) of a black body material and subjecting the black box with the wafer therein to an RTA. In a preferred embodiment the RTA comprises (a) a pre-anneal step which includes heating to a temperature and for a period sufficient to preheat the wafer so as to reduce thermal shock due to a main annealing step, (b) the main annealing step being at a temperature and for a period sufficient to remove damage caused to said surface by the dopant implantation and to activate implanted dopant, and (c) a post-anneal step carried out at a temperature and for a period sufficient to relieve stresses which may result from the main annealing step. The combined use of the RTA and the black box leads to wafers substantially free of slip lines and with reproducibly high mobilities and uniform activation.

Inventors

  • 👤 Karen A. Grim
  • 👤 Bertram Schwartz
  • 👤 Shobha Singh
  • 👤 Legrand G. Van Uitert
  • 👤 George J. Zydzik

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-29 08:29
CPC Classifications
H; H10; H10P; H10P72/00; H10P72/04; H10P72/0431; H10P72/0436; H10P95/00; H10P95/90; H10P95/904; Y; Y10; Y10S; Y10S148/00; Y10S148/003; Y10S148/071

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 77 words
Appartus for use in a semiconductor annealing process CHARACTERISED BY components of black-body material stable under annealing conditions, said components including a base (10), an annular guard ring (11) and a lid (12) such that when the guard ring is positioned on the base and the lid is positioned on the guard ring, the components form a container (hereinafter referred to as a "black-box") containing a cavity for fully enclosing a semiconductor wafer (1) to be annealed.
Claim 2
Dependent Claim 77 words
Appartus for use in a semiconductor annealing process CHARACTERISED BY components of black-body material stable under annealing conditions, said components including a base (10), an annular guard ring (11) and a lid (12) such that when the guard ring is positioned on the base and the lid is positioned on the guard ring, the components form a container (hereinafter referred to as a "black-box") containing a cavity for fully enclosing a semiconductor wafer (1) to be annealed.
Claim 3
Dependent Claim 15 words
Apparatus as claimed in claim 1 in which said black-body material comprises graphite or silicon.
Claim 4
Dependent Claim 32 words
Apparatus as claimed in claim 1 or claim 2 in which surfaces of the said components which constitute the internal surfaces of the black-box are encapsulated with a layer of encapsulating material.
Claim 5
Dependent Claim 37 words
Apparatus as claimed in claim 3 in which said encapsulating material is selected from the group consisting of phosphosilicate glass, borosilicate glass, SiO₂, and a glass consisting of 3% B₂,O₃, 1% Al₂O₃ and 96% SiO₂ by weight.
Claim 6
Dependent Claim 19 words
Apparatus as claimed in claim 4 in which the encapsulating material comprises phosphosilicate glass comprising 2-10 mole percent P₂O₅.
Claim 7
Dependent Claim 43 words
A semiconductor fabrication process comprising subjecting a semiconductor wafer to an annealing procedure CHARACTERISED IN THAT the annealing procedure is carried out with the wafer enclosed in the cavity of a black-box constituted by apparatus as claimed in any of the preceding claims.
Claim 8
Dependent Claim 17 words
A process as claimed in claim 6 wherein the annealing procedure is a rapid thermal anneal (RTA).
Claim 9
Dependent Claim 78 words
A process as claimed in claim 7 in which said RTA includes in sequence, a pre-anneal step, a main annealing step, and a post-anneal step, the pre-anneal step being conducted at a temperature and for a period sufficient to reduce any thermal shock to the semiconductor material which may result from the main-annealing step, and the post-anneal step being conducted at a temperature and for a period sufficient to relieve stresses which may result from the main-annealing step.
Claim 10
Dependent Claim 117 words
A process as claimed in claim 8 in which said compound semiconductor material comprises GaAs, said RTA includes exposure of the black-box with the wafer therein in succession to the pre-anneal step in the temperature range 625 to 675 0 C for a period in the range 20 to 40 seconds, the main annealing step at a peak temperature within the range 900 to 1000 0 C for a period in the range 5 to 20 seconds, and the post-anneal step in the temperature range 825 to 875 0 C for a period in the range 25 to 35 seconds, followed by cool down at a rate in the range 5 to 50 0 C per second.
Claim 11
Dependent Claim 22 words
A process as claimed in claim 9 in which said cool-down is at a rate not exceeding 30 0 C per second.
Claim 12
Dependent Claim 22 words
A process as claimed in claim 10 in which said cool-down is at a rate of about 10 0 C per second.
Claim 13
Dependent Claim 70 words
A process as claimed in any of claims 6 to 11 wherein the wafer has dopant ions implanted into at least one selected area of at least one surface thereof and a layer of encapsulating material (2) over said surface, said annealing procedure being conducted at a temperature and for a period sufficient to remove damage caused to the said surface by the implantation and to activate said dopant ions.
Claim 14
Dependent Claim 39 words
A process as claimed in claim 12 in which said encapsulating material on said wafer surface comprises a glass selected from phosphosilicate glass, borosilicate glass and a glass consisting of 3% B₂O₃, 1% Al₂O₃ and 96% SiO₂ by weight.
Claim 15
Dependent Claim 24 words
A process as claimed in claim 13 in which said encapsulating material on said wafer surface comprises phosphosilicate glass comprising 2-10 mole percent P₂O₅.

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