EP0399240A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1990-04-26
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Granted: —
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Expires: 2010-04-26
Abstract
Abstract A semiconductor memory device such as dynamic random access memories (DRAMs) comprises a word line drive circuit (16) provided with two MOS transistors and a word line to which a word line drive signal (C) is supplied, a substrate bias generation circuit (11) for applying a bias voltage to a semiconductor substrate (10) for MOS transistors, a burn-in mode detection circuit (14) for detecting a burn-in test mode signal, and a substrate bias control circuit (15) for controlling the substrate bias generation circuit (11). When the semiconductor memory device is subjected to a burn-in test, the power supply level Vcc is increased to raise the voltage of the word line drive signal (C) as compared to that at a normal operation. Accordingly, a high level word line drive signal (C) will be applied to cell transistors, thereby performing correct screening thereof.
Inventors
- 👤 Mitsuru C/O Intellectual Property Div. Shimizu
- 👤 Syuso C/O Intellectual Property Div. Fujii
- 👤 Shozo C/O Intellectual Property Div. Saito
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 05:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C29/00; G11C29/04; G11C29/50; G11C5/00; G11C5/14; G11C5/145; G11C5/146; G11C8/00; G11C8/08; G06; G06F; G06F2201/00; G06F2201/81
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
233 words
A semiconductor memory device including: a word line drive circuit (16) including a first MOS transistor (TN1) having two terminals and a gate, a row decode output signal (A) entering said one terminal of said first MOS transistor (TN1), a desired electric potential (Vcc) being applied to said gate of said first MOS transistor (TN1), a second MOS transistor (TN2) having two terminals and a gate, said gate of said second MOS transistor (TN2) being connected to the other terminal of said first MOS transistor (TN1), a word line drive control signal (WDRV) being applied to said one terminal of said second MOS transistor (TN2), and a word line (WL) connected to the other terminal of said second MOS transistor (TN2), a word line drive signal (C) fed from the other terminal of said second MOS transistor (TN2) being supplied to said word line (WL), and a substrate bias generation circuit (11) for applying a bias voltage to a semiconductor substrate (10), said MOS transistors (TN1, TN2) being provided in said semiconductor substrate (10), characterized by comprising: a burn-in mode detection circuit (14) for detecting a burn-in test mode signal input supplied from an external device, and a substrate bias control circuit (15) for controlling said substrate bias generation circuit (11) so as to lower said bias voltage according to a burn-in test mode detection output of said burn-in mode detection circuit (14).
Claim 2
Dependent Claim
233 words
A semiconductor memory device including: a word line drive circuit (16) including a first MOS transistor (TN1) having two terminals and a gate, a row decode output signal (A) entering said one terminal of said first MOS transistor (TN1), a desired electric potential (Vcc) being applied to said gate of said first MOS transistor (TN1), a second MOS transistor (TN2) having two terminals and a gate, said gate of said second MOS transistor (TN2) being connected to the other terminal of said first MOS transistor (TN1), a word line drive control signal (WDRV) being applied to said one terminal of said second MOS transistor (TN2), and a word line (WL) connected to the other terminal of said second MOS transistor (TN2), a word line drive signal (C) fed from the other terminal of said second MOS transistor (TN2) being supplied to said word line (WL), and a substrate bias generation circuit (11) for applying a bias voltage to a semiconductor substrate (10), said MOS transistors (TN1, TN2) being provided in said semiconductor substrate (10), characterized by comprising: a burn-in mode detection circuit (14) for detecting a burn-in test mode signal input supplied from an external device, and a substrate bias control circuit (15) for controlling said substrate bias generation circuit (11) so as to lower said bias voltage according to a burn-in test mode detection output of said burn-in mode detection circuit (14).
Claim 3
Dependent Claim
70 words
The device according to claim 1, characterized in that a first substrate potential detection circuit (12) for detecting an electric potential of said semiconductor substrate (10) and a first switching circuit (13) for on/off controlling an operation of said substrate bias generation circuit (11) according to an output of said first substrate potential detection circuit (12) are connected between said semiconductor substrate (10) and said substrate bias generation circuit (11).
Claim 4
Dependent Claim
90 words
The device according to claim 1, characterized in that said substrate bias control circuit (15) includes: a second substrate potential detection circuit (17) for detecting a substrate potential to be set at a burn-in test; and a second switching circuit (18) controlled to an enabled condition according to said burn-in test mode detection output of said burn-in mode detection circuit (14), said second switching circuit (18) on/off controlling an operation of said substrate bias generation circuit (11) according to a detected output of said second substrate potential detection circuit (17).
References Cited (Backward Citations)
No citation records indexed.
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