EP0398690A2
Expired / Lapsed
EP
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Circuitry implementing the Viterbi algorithm
Assignee: Nokia Oyj
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Filing: 1990-05-16
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Granted: —
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Expires: 2010-05-16
Abstract
Abstract The invention concerns a circuitry implementing the Viterbi algorithm at such a trellis at which each state may be reached along two alternative paths. The states of the bits of a defined time interval are processed utilizing the inventive circuitry in serial form for indicating the symbol including one bit and/or several bits. The invention may be applied, for instance, in the GSM mobile telephone, in which, by the aid of the invention, the signal processing circuits may be saved significantly.
Inventors
- 👤 Jussi Silander
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 17:58
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/37; H03M13/39; H03M13/41
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
51 words
A circuitry implementing the Viterbi algorithm in a trellis in which each state may be entered along two alternative paths, characterized in that the states of the bits of a defined time interval are processed with the circuitry in serial form for indicating the symbol of a bit and/or several bits.
Claim 2
Dependent Claim
51 words
A circuitry implementing the Viterbi algorithm in a trellis in which each state may be entered along two alternative paths, characterized in that the states of the bits of a defined time interval are processed with the circuitry in serial form for indicating the symbol of a bit and/or several bits.
Claim 3
Dependent Claim
162 words
A circuitry according to claim 1, characterized in that it comprises circuits, in which (a) for each bit (BIT k ) the sum of the transition values (TRANS k ) of the values of the cumulative values (CUM(i)) of the states at each moment and of the changes between the bits (BIT k and BIT k+1 ) are produced in addition circuits (ADD), (b) two addition values of each state are compared in a subtraction circuit (SUB), (c) the result of the comparison (DF) is stored in a trace back path table (TB), and (d) a new cumulative value (NEW) of the processed bit is selected utilizing a selection circuit which is stored in the table of cumulative values (CT), whereby the operation (items a through d) is repeated regarding each of the 16 potential states of a bit, and whereby in the circuitry the entire operation sequence presented above is repeated for each bit in order to determine the return path.
Claim 4
Dependent Claim
86 words
A circuitry according to claim 2, characterized in that it comprises furthermore (e) an indication circuit of a return path, in which on the basis of the bit-specific data (MSBT(T)) read in the trace back path table the address (LSB) of an address location is calculated at each bit of the time interval from which the most probable value of the bit or symbol at a moment can be read, whereby the bits or symbols of a time interval are indicated starting from the last one.
Claim 5
Dependent Claim
17 words
A use of the circuitry according to claim 3 for indicating the bits of a signal flow.
Claim 6
Dependent Claim
18 words
A use of the circuitry according to claim 3 for decoding the convolutional code of a signal flow.
Claim 7
Dependent Claim
28 words
A use of a circuitry according to claim 3 both for indicating rhe bits of a signal flow and for decoding the convolutional code in the same apparatus.
Claim 8
Dependent Claim
21 words
A circuitry according to claim 2 or 3, characterized in that it is implemented as a part of an integrated circuit.
Claim 9
Dependent Claim
28 words
A use of a circuitry according to any one of claims 1, 2, 3 or 7 in a mobile telephone of the general European digital mobile telephone system.
References Cited (Backward Citations)
No citation records indexed.
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