Serializing system between vector instruction and scalar instruction in data processing system

Claim 2

A data processing system, comprising a scalar unit (1), a vector unit (2), and a storage, said scalar unit (1) receives scalar instructions and vector instructions, carries out scalar data processing in accordance with said scalar instruction, and transfers said vector instruction to said vector unit (2), said vector unit (2) receives said vector instruction from said scalar unit (1), carries out vector data processing in accordance with said vector instruction, and comprises a post pending signal generating means (81- 86, 201) for generating a post pending signal which is made active when a post instruction is received in the vector unit (2), and is made inactive when a right to access said storage is obtained for reading or storing a last element through operations for all vector instructions preceding the post instruction, and said scalar unit (1) further comprising, a wait instruction detecting means for detecting a transfer of a wait instruction to said vector unit (2), and an interlock control means (111-114) for suspending execution of instructions which follow a wait instruction which is detected in said wait instruction detecting means and each including an operation to access said storage until said post pending signals changes from active to inactive.

Claim 3

A data processing system, comprising a scalar unit (1), a vector unit (2), and a storage, said scalar unit (1) receives scalar instructions and vector instructions, carries out scalar data processing in accordance with said scalar instruction, and transfers said vector instruction to said vector unit (2), said vector unit (2) receives said vector instruction from said scalar unit (1), carries out vector data processing in accordance with said vector instruction, and comprises a first post pending signal generating means (81- 86, 201) for generating a first post pending signal which is made active when a post instruction is received from the scalar unit (1) and is made inactive when a right to access said storage is obtained for reading or storing a last element through operations for all vector instructions preceding the post instruction, and said scalar unit (1) further comprising, a post instruction detecting means for detecting a transfer of a post instruction to said vector unit (2), a wait instruction detecting means for detecting a transfer of a wait instruction to said vector unit (2), a second post pending signal generating means (91-99, 101-105) which receives the output of said post instruction detecting means and said first post pending signal, and generates a second post pending signal which is made active when a post instruction is transferred to the vector unit (2) and is made inactive when said first post pending signal becomes inactive, and an interlock control means (111-114) for suspending execution of instructions which follow the wait instruction which is detected in said wait instruction detecting means and each including an operation to access said storage, while said second post pending signals is active.

Claim 4

A data processing system, comprising a scalar unit (1), a vector unit (2), and a storage, said scalar unit (1) receives scalar instructions and vector instructions, carries out scalar data processing in accordance with said scalar instruction, and transfers said vector instruction to said vector unit (2), said vector unit (2) receives said vector instruction from said scalar unit (1), carries out vector data processing in accordance with said vector instruction, and comprises a first post pending signal generating means (81- 86, 201) for generating a first post pending signal which is made active when a post instruction is received from the scalar unit (1) and is made inactive when a right to access said storage is obtained for reading or storing a last element through operations for all vector instructions preceding the post instruction, and said scalar unit (1) further comprising, a post instruction detecting means for detecting a transfer of a post instruction to said vector unit (2), a wait instruction detecting means for detecting a transfer of a wait instruction to said vector unit (2), a second post pending signal generating means (91-99, 101-105) which receives the output of said post instruction detecting means and said first post pending signal, and generates a second post pending signal which is made active when a post instruction is transferred to the vector unit (2) and is made inactive when said first post pending signal becomes inactive, and an interlock control means (111-114) for suspending execution of instructions which follow the wait instruction which is detected in said wait instruction detecting means and each including an operation to access said storage, while said second post pending signals is active.

Claim 5

A data processing system according to claim 2, wherein said first post pending signal generating means (81- 86, 201) further comprises, a plurality of flag means which are provided corresponding to a plurality of stages from a vector instruction fetch stage to a vector instruction start stage for vector instructions, for indicating that a post instruction is currently processed in the respective stages, an after-start stages control means (201) for controlling an execution of a vector instruction after its start, including operations to access said storage for a vector instruction, and comprising a last memory access detecting means (44) for detecting that a right to access said storage is obtained for reading or storing a last element through the execution of the vector instruction, and outputting a last memory access signal which indicates said detection, and a first gate means (86) which receives all the outputs of said plurality of flag means and said last memory access signal, and outputs said first post pending signal which is made active when either of the outputs of said plurality of flag means is active and the last memory access signal is inactive, and is made inactive when neither of the outputs of said plurality of flag means is active and the last memory access signal is active.

Claim 6

A data processing system according to claim 3, wherein said second post pending signal generating means (91-99, 101-105) further comprises, a status register (92) which is set when an operation for a post instruction is released from an address calculation stage in the scalar unit (1), outputs said second post pending signal, and is reset by a reset signal, a shift register (93-99) comprised of a plurality of registers which are provided corresponding to a plurality of operation stages for instructions processed in said scalar unit (1) and a predetermined delay, where the input of the shift register (93-99) is the same as the input of said status register (92), and said delay is predetermined so that activeness of said second post pending signal continues at least from the time a post instruction is detected in said post instruction detecting means until an active first post pending signal responding to the same post instruction is received in the scalar unit (1), and a second gate means (105) which receives all the outputs of said plurality of registers in said shift register (93-99) and said first post pending signal from said vector unit (2), and outputs said reset signal to said status register (92), where said reset signal is made active when neither of the inputs of the second gate means (105) is active.

Claim 7

A data processing system, comprising a scalar unit (1), a vector unit (2), a storage, and a memory control unit (14), said scalar unit (1) receives both a scalar instruction and a vector instruction, carries out scalar data processing in accordance with said scalar instruction, transfers said vector instruction to said vector unit (2), and sends requests for accessing said storage to said memory control unit (14) during said scalar data processing in accordance with said scalar instruction, said vector unit (2) receives said vector instruction from said scalar unit (1), carries out vector data processing in accordance with said vector instruction, and sends requests for accessing said storage to said memory control unit (14) during said vector data processing in accordance with said vector instruction, said memory control unit (14) receives said requests for accessing the storage from said scalar unit (1) and said vector unit (2), carries out operations to access said storage for the received requests, and comprises a priority control means for outputting an active memory access acknowledge signal responding to one of the received requests for giving a right to access the main storage to a corresponding one of the scalar unit (1) and a vector unit (2), said vector unit (2) further comprising a first post pending signal generating means (81- 86, 201) for generating a first post pending signal which is made active when a post instruction is received from the scalar unit (1) and is made inactive when a right to access said storage is obtained for reading or storing a last element through operations for all vector instructions preceding the post instruction, and said scalar unit (1) further comprising, a post instruction detecting means for detecting a transfer of a post instruction to said vector unit (2), a wait instruction detecting means for detecting a transfer of a wait instruction to said vector unit (2), a second post pending signal generating means (91-99, 101-105) which receives the output of said post instruction detecting means and said first post pending signal, and generates a second post pending signal which is made active when a post instruction is transferred to the vector unit (2) and is made inactive when said first post pending signal becomes inactive, and an interlock control means (111-114) for suspending execution of instructions which follow the wait instruction which is detected in said wait instruction detecting means and each including an operation to access said storage, while said second post pending signal is active.

Claim 8

A data processing system, comprising a scalar unit (1), a vector unit (2), a storage, and a memory control unit (14), said scalar unit (1) receives both a scalar instruction and a vector instruction, carries out scalar data processing in accordance with said scalar instruction, transfers said vector instruction to said vector unit (2), and sends requests for accessing said storage to said memory control unit (14) during said scalar data processing in accordance with said scalar instruction, said vector unit (2) receives said vector instruction from said scalar unit (1), carries out vector data processing in accordance with said vector instruction, and sends requests for accessing said storage to said memory control unit (14) during said vector data processing in accordance with said vector instruction, said memory control unit (14) receives said requests for accessing the storage from said scalar unit (1) and said vector unit (2), carries out operations to access said storage for the received requests, and comprises a priority control means for outputting an active memory access acknowledge signal responding to one of the received requests for giving a right to access the main storage to a corresponding one of the scalar unit (1) and a vector unit (2), said vector unit (2) further comprising a first post pending signal generating means (81- 86, 201) for generating a first post pending signal which is made active when a post instruction is received from the scalar unit (1) and is made inactive when a right to access said storage is obtained for reading or storing a last element through operations for all vector instructions preceding the post instruction, and said scalar unit (1) further comprising, a post instruction detecting means for detecting a transfer of a post instruction to said vector unit (2), a wait instruction detecting means for detecting a transfer of a wait instruction to said vector unit (2), a second post pending signal generating means (91-99, 101-105) which receives the output of said post instruction detecting means and said first post pending signal, and generates a second post pending signal which is made active when a post instruction is transferred to the vector unit (2) and is made inactive when said first post pending signal becomes inactive, and an interlock control means (111-114) for suspending execution of instructions which follow the wait instruction which is detected in said wait instruction detecting means and each including an operation to access said storage, while said second post pending signal is active.

Claim 9

A data processing system according to claim 5, wherein said first post pending signal generating means (81- 86, 201) further comprises, a plurality of flag means which are provided corresponding to a plurality of stages from a vector instruction fetch stage to a vector instruction start stage for vector instructions, for indicating that a post instruction is currently processed in the respective stages, an after-start stages control means (201) for controlling an execution of a vector instruction after its start, including operations to access said storage for a vector instruction, and comprising a last memory access detecting means (44) for detecting that a right to access said storage is obtained for reading or storing a last element through the execution of the vector instruction, and outputting a last memory access signal which indicates said detection, and a first gate means (86) which receives all the outputs of said plurality of flag means and said last memory access signal, and outputs said first post pending signal which is made active when either of the outputs of said plurality of flag means is active and the last memory access signal is inactive, and is made inactive when neither of the outputs of said plurality of flag means is active and the last memory access signal is active.

Claim 10

A data processing system according to claim 6, wherein said second post pending signal generating means (91-99, 101-105) further comprises, a status register (92) which is set when an operation for the post instruction is released from an address calculation stage in the scalar unit (1), outputs said second post pending signal, and is reset by a reset signal, a shift register (93-99) comprised of a plurality of registers which are provided corresponding to a plurality of operation stages for instructions processed in said scalar unit (1) and a predetermined delay, where the input of the shift register (93-99) is the same as the input of said status register (92), and said delay is predetermined so that activeness of said second post pending signal continues at least from the time a post instruction is detected in said post instruction detecting means until an active first post pending signal responding to the same post instruction is received in the scalar unit (1), and a second gate means (105) which receives all the outputs of said plurality of registers in said shift register (93-99) and said second post pending signal from said vector unit (2), and generates said reset signal to said status register (92), where said reset signal is made active when neither of the inputs of the second gate means (105) is active.

Claim 11

A data processing system, comprising a scalar unit (1), a vector unit (2), a storage, and a memory control unit (14), said scalar unit (1) receives both a scalar instruction and a vector instruction, carries out scalar data processing in accordance with said scalar instruction, transfers said vector instruction to said vector unit (2), and requests said memory control unit (14) to access said storage during said scalar data processing in accordance with said scalar instruction, said vector unit (2) receives said vector instruction from said scalar unit (1), carries out vector data processing in accordance with said vector instruction, and sends requests for accessing said storage to said memory control unit (14) during said vector data processing in accordance with said vector instruction, said memory control unit (14) receives said requests for accessing the storage from said scalar unit (1) and said vector unit (2), carries out operations to access said storage for the received requests, and comprises, a buffer memory invalidation address storing means (71) for temporarily storing one or more addresses to which addresses in said storage access operations are carried out, a buffer memory invalidation address transferring means for transferring said addresses stored in said buffer memory invalidation address storing means (71) to said scalar unit (1), and removing the transferred addresses from the buffer memory invalidation address storing means (71), a transfer complete signal generating means (66) for generating a transfer complete signal which indicates that all addresses stored in said buffer memory invalidation address storing means (71) have been transferred to said scalar unit (1) when active, and a priority control means for outputting an active memory access acknowledge signal responding to one of the received requests for giving a right to access the main storage to a corresponding one of the scalar unit (1) and a vector unit (2), said vector unit (2) further comprising, an after-start stages control means (201) for controlling an execution of a vector instruction after its start, including operations to access said storage for a vector instruction, and comprising a last memory access detecting means (44) for detecting that a right to access said storage is obtained for reading or storing a last element through the execution of the vector instruction, and outputting a last memory access signal which indicates said detection, and a first post pending signal generating means (81- 86, 201) for generating a first post pending signal which is made active when a post instruction is received from the scalar unit (1), and is made inactive when an active transfer complete signal is received from said memory control unit (14) and an active last memory access signal from said last memory access detecting means (44), said scalar unit (1) further comprising, a buffer memory for temporarily storing a portion of data of said main storage, a buffer memory invalidation means for invalidating data in said buffer memory using the addresses which are transferred by said buffer memory invalidation address transferring means, when the address of the data in the buffer memory corresponds to the address in the storage to which a write operation from the vector unit (2) has been carried out, a post instruction detecting means for detecting a transfer of a post instruction to said vector unit (2), a wait instruction detecting means for detecting a transfer of a wait instruction to said vector unit (2), a second post pending signal generating means (91-99, 101-105) which receives the output of said post instruction detecting means and said first post pending signal, and generates a second post pending signal which is made active when a post instruction is transferred to the vector unit (2) and is made inactive when said first post pending signal becomes inactive, and an interlock control means (111-114) for suspending execution of instructions which follow the wait instruction which is detected in said wait instruction detecting means and each including an operation to access said storage, while said second post pending signal is active.

Claim 12

A data processing system, comprising a scalar unit (1), a vector unit (2), a storage, and a memory control unit (14), said scalar unit (1) receives both a scalar instruction and a vector instruction, carries out scalar data processing in accordance with said scalar instruction, transfers said vector instruction to said vector unit (2), and requests said memory control unit (14) to access said storage during said scalar data processing in accordance with said scalar instruction, said vector unit (2) receives said vector instruction from said scalar unit (1), carries out vector data processing in accordance with said vector instruction, and sends requests for accessing said storage to said memory control unit (14) during said vector data processing in accordance with said vector instruction, said memory control unit (14) receives said requests for accessing the storage from said scalar unit (1) and said vector unit (2), carries out operations to access said storage for the received requests, and comprises, a buffer memory invalidation address storing means (71) for temporarily storing one or more addresses to which addresses in said storage access operations are carried out, a buffer memory invalidation address transferring means for transferring said addresses stored in said buffer memory invalidation address storing means (71) to said scalar unit (1), and removing the transferred addresses from the buffer memory invalidation address storing means (71), a transfer complete signal generating means (66) for generating a transfer complete signal which indicates that all addresses stored in said buffer memory invalidation address storing means (71) have been transferred to said scalar unit (1) when active, and a priority control means for outputting an active memory access acknowledge signal responding to one of the received requests for giving a right to access the main storage to a corresponding one of the scalar unit (1) and a vector unit (2), said vector unit (2) further comprising, an after-start stages control means (201) for controlling an execution of a vector instruction after its start, including operations to access said storage for a vector instruction, and comprising a last memory access detecting means (44) for detecting that a right to access said storage is obtained for reading or storing a last element through the execution of the vector instruction, and outputting a last memory access signal which indicates said detection, and a first post pending signal generating means (81- 86, 201) for generating a first post pending signal which is made active when a post instruction is received from the scalar unit (1), and is made inactive when an active transfer complete signal is received from said memory control unit (14) and an active last memory access signal from said last memory access detecting means (44), said scalar unit (1) further comprising, a buffer memory for temporarily storing a portion of data of said main storage, a buffer memory invalidation means for invalidating data in said buffer memory using the addresses which are transferred by said buffer memory invalidation address transferring means, when the address of the data in the buffer memory corresponds to the address in the storage to which a write operation from the vector unit (2) has been carried out, a post instruction detecting means for detecting a transfer of a post instruction to said vector unit (2), a wait instruction detecting means for detecting a transfer of a wait instruction to said vector unit (2), a second post pending signal generating means (91-99, 101-105) which receives the output of said post instruction detecting means and said first post pending signal, and generates a second post pending signal which is made active when a post instruction is transferred to the vector unit (2) and is made inactive when said first post pending signal becomes inactive, and an interlock control means (111-114) for suspending execution of instructions which follow the wait instruction which is detected in said wait instruction detecting means and each including an operation to access said storage, while said second post pending signal is active.

Claim 13

A data processing system according to claim 8, wherein said first post pending signal generating means (81- 86, 201) further comprises, a plurality of flag means which are provided corresponding to a plurality of operation stages for instructions processed in said vector unit (2), for indicating that a post instruction is processed in the respective stages, and a first gate means (86) which receives all the outputs of said plurality of flag means and said trans­fer complete signal from said memory control unit (14) and said last memory access signal from said last memory access detecting means (44), and outputs said first post pending signal which is made active when either of the outputs of said plurality of flag means is active and either of the transfer complete signal and the last memory access signal are inactive, and is made inactive when neither of the outputs of said plurality of flag means is active and both the transfer complete signal and the last memory access signal are active.

Claim 14

A data processing system according to claim 9, wherein said second post pending signal generating means (91-99, 101-105) further comprises, a status register (92) which is set when an operation for the post instruction is released from an address calculation stage in the scalar unit (1), outputs said second post pending signal, and is reset by a reset signal, a shift register (93-99) comprised of a plurality of registers which are provided corresponding to a plurality of operation stages for instructions processed in said scalar unit (1) and a predetermined delay, where the input of the shift register (93-99) is the same as the input of said status register (92), and said delay is predetermined so that activeness of said second post pending signal continues at least from the time a post instruction is detected in said post instruction detecting means until an active first post pending signal responding to the same post instruction is received in the scalar unit (1), and a second gate means (105) which receives all the outputs of said plurality of registers in said shift register (93-99) and said first post pending signal from said vector unit (2), and generates said reset signal to said status register (92), where said reset signal is made active when neither of the inputs of the second gate means (105) is active.

Claim 15

A data processing system according to claim 8, wherein said memory control unit (14) further comprises, an address table (55) for storing addresses of data which is currently stored in said buffer memory, and a comparing means (56) for comparing the addresses stored in said buffer memory invalidation address storing means (71) with the addresses stored in said address table (55), said buffer memory invalidation address transferring means transfers an address stored in said buffer memory invalidation address storing means (71) to said scalar unit (1), when the address stored in said buffer memory invalidation address storing means (71) coincides with an address stored in said address table (55).