EP0398523A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A device for data i/o and execution support in digital processors
Assignee: Hitachi Ltd
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Filing: 1990-04-25
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Granted: —
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Expires: 2010-04-25
Abstract
Abstract A device for simultaneous data input and output and execution support in digital processors including a plurality of controllable input and output ports (6,8,12) for inputting and outputting data from the device, a data cache memory (10) which is selectively connectable to each of the plurality of input and output ports (6,8,12) and a controller (20) for controlling the plurality of input and output ports (6,8,12) and the data cache memory (10) for effecting a transfer of data between any of the plurality of input and output ports (6,8,12) or the data cache memory (10).
Inventors
- 👤 Chandravadan N. Patel
- 👤 Richard Wm. Blasco
- 👤 Kenneth M. Chan
- 👤 Shieh C. Chen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 04:52
CPC Classifications
G; G06; G06F; G06F17/00; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0853; G06F12/0855; G06F12/0857
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
123 words
A device for data input and output and execution support in a digital processor, comprising: a plurality of input/output interfaces for providing a plurality of controllable input/output ports for inputting and outputting data from said device, each of said plurality of input/output interfaces being individually controllable and operable without control signals from sources external to said device; a data cache memory selectively couplable to each of said plurality on input/output interfaces; and a controlling means for controlling said plurality of input/output interfaces and said data cache memory for effecting a transfer of data between any of said plurality of input/output devices or said data cache memory, the controlling means being arranged to effect data transfer simultaneously with program execution in a digital processor.
Claim 2
Independent Claim
123 words
A device for data input and output and execution support in a digital processor, comprising: a plurality of input/output interfaces for providing a plurality of controllable input/output ports for inputting and outputting data from said device, each of said plurality of input/output interfaces being individually controllable and operable without control signals from sources external to said device; a data cache memory selectively couplable to each of said plurality on input/output interfaces; and a controlling means for controlling said plurality of input/output interfaces and said data cache memory for effecting a transfer of data between any of said plurality of input/output devices or said data cache memory, the controlling means being arranged to effect data transfer simultaneously with program execution in a digital processor.
Claim 3
Dependent Claim
46 words
A device according to claim 1, wherein said plurality of data input/output interfaces are selected from the group consisting of host central processing unit input and output interfaces, serial input and output interfaces, external memory input and output interfaces and parallel data input and output interfaces.
Claim 4
Dependent Claim
37 words
A device according to claim 1 or claim 2, wherein each input/output interface has a pair of serial/parallel converters between the input and output of the interface, the serial/parallel converters being arranged to convert in opposite senses.
Claim 5
Independent Claim
53 words
A device according to any one of the preceding claims, wherein the data cache memory includes a page memory, and there is at least one bus connecting the data cache memory to the plurality of input/output interfaces whereby data transfer is effectable from the data cache memory to the interfaces via the bus(es).
Claim 6
Dependent Claim
17 words
A device according to claim 4 having an input/output register between the page memory and the bus(es).
Claim 7
Independent Claim
124 words
A device for data input and output and execution support in a digital processor, comprising: a plurality of input/output interfaces for providing a plurality of controllable input/output ports for inputting and outputting data from said device, each of said plurality of input/output interfaces being individually controllable and operable without control signals from sources external to said device; a data cache memory selectively couplable to eacch of said plurality on input/output interfaces; and a controlling means for controlling said plurality of input/output interfaces and said data cache memory for effecting a transfer of data between any of said plurality of input/output devices or said data cache memory, the controlling means being arranged to effect data transfer in parallel with program execution in a digital processor.
Claim 8
Independent Claim
124 words
A device for data input and output and execution support in a digital processor, comprising: a plurality of input/output interfaces for providing a plurality of controllable input/output ports for inputting and outputting data from said device, each of said plurality of input/output interfaces being individually controllable and operable without control signals from sources external to said device; a data cache memory selectively couplable to eacch of said plurality on input/output interfaces; and a controlling means for controlling said plurality of input/output interfaces and said data cache memory for effecting a transfer of data between any of said plurality of input/output devices or said data cache memory, the controlling means being arranged to effect data transfer in parallel with program execution in a digital processor.
Claim 9
Dependent Claim
31 words
The combination of a digital processor and a device according to any one of the preceding claims, arranged for simultaneous data input and output and execution support in the digital processor.
Claim 10
Independent Claim
131 words
A method of operating the combination of a digital processor and a device for data input and output and execution support in that processor; the device comprising a plurality of input/output interfaces for providing a plurality of controllable input/output ports for inputting and outputting data from said device, each of said plurality of input/output interfaces being individually controllable and operable without control signals from sources external to said device; a data cache memory selectively couplable to eacch of said plurality on input/output interfaces; and a controlling means for controlling said plurality of input/output interfaces and said data cache memory for effecting a transfer of data between any of said plurality of input/output devices or said data cache memory, wherein data transfer is effected simultaneously with program execution on the digital processor.
Claim 11
Independent Claim
131 words
A method of operating the combination of a digital processor and a device for data input and output and execution support in that processor; the device comprising a plurality of input/output interfaces for providing a plurality of controllable input/output ports for inputting and outputting data from said device, each of said plurality of input/output interfaces being individually controllable and operable without control signals from sources external to said device; a data cache memory selectively couplable to eacch of said plurality on input/output interfaces; and a controlling means for controlling said plurality of input/output interfaces and said data cache memory for effecting a transfer of data between any of said plurality of input/output devices or said data cache memory, wherein data transfer is effected simultaneously with program execution on the digital processor.
References Cited (Backward Citations)
No citation records indexed.
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