Multiprocessor type time varying image encoding system and image processor

Claim 2

A multiprocessor type time varying image encoding system comprising: a plurality of digital signal processor (DSP) modules (DMM's) disposed in parallel, each DMM including a DSP executing encoding according to an encoding program, a local memory connected to a local bus of said DSP, and an inter­rupt control unit which delivers to said DSP interrupt signals sent from a control bus while arbitrating between them and which also decodes an address and data received from the local bus of said DSP to generate an interrupt signal and sends it to said control bus; a plurality of common memories connected to said DMM's to store locally decoded data or data which is being encoded and parameters; an input frame memory constituted of a plurality of buffers, one side of which is opened up for a circuit for writing input data, and the other side of which is opened up for said DMM's, so that writing and reading operations can be executed asynchronously; a task control unit instructing each of said DMM's about the position of a processing block assigned thereto and the contents of a processing task to be executed by commands through said control bus; and a task table for storing information required for said task control unit to control said DMM'S, said task control unit dividing an image into a plurality of blocks, retrieving said task table to determine an optimal block to be processed and processing task to be executed for each DMM and assigning said DMM's processing tasks substantially equally to execute encoding.

Claim 3

A load distributing multiprocessor type time varying image encoding system having a plurality of digital signal processor (DSP) modules (DMM's) each including a DSP execut­ing encoding according to a program and a DSP peripheral circuit, said DMM's being arranged in parallel to execute encoding under control such that the amounts of computation assigned to said DSP's are equalized with each other, wherein the improvement comprises: common memories includ­ing an input frame memory for storing an input image and n memories for storing locally decoded data, feedback data, coded data, etc., said n+1 common memories respectively having independent memory buses which have addresses and data separated from each other; a task control unit control­ling load distribution to said DSP's; a task table for sorting information needed for said task control unit to effect load distribution to said DSP's; and a memory bus control table for storing information needed for said task control unit to effect arbitration between said memory buses, said task control unit dividing an image into a plurality of blocks, retrieving said task table to determine an optimal block to be processed and processing task to be executed for each DMM and assigning said DMM's processing tasks substantially equally to execute encoding, said task control unit further arbitrating between common memory access requests from said DSP's and determining an order of priority by referring to said memory bus control table, thereby arbitrating between said memory buses.

Claim 4

A load distributing multiprocessor type time varying image encoding system having a plurality of digital signal processor (DSP) modules (DMM's) each including a DSP execut­ing encoding according to a program and a DSP peripheral circuit, said DMM's being arranged in parallel to execute encoding under control such that the amounts of computation assigned to said DSP's are equalized with each other, wherein the improvement comprises: common memories includ­ing an input frame memory for storing an input image and n memories for storing locally decoded data, feedback data, coded data, etc., said n+1 common memories respectively having independent memory buses which have addresses and data separated from each other; a task control unit control­ling load distribution to said DSP's; a task table for sorting information needed for said task control unit to effect load distribution to said DSP's; and a memory bus control table for storing information needed for said task control unit to effect arbitration between said memory buses, said task control unit dividing an image into a plurality of blocks, retrieving said task table to determine an optimal block to be processed and processing task to be executed for each DMM and assigning said DMM's processing tasks substantially equally to execute encoding, said task control unit further arbitrating between common memory access requests from said DSP's and determining an order of priority by referring to said memory bus control table, thereby arbitrating between said memory buses.

Claim 5

A bus control method for a system in which a plurality of digital signal processors are connected to a common memory which can be accessed by two or more processors in a time-division manner, wherein, when any of said processors needs to access said common memory, it outputs a common memory access request a predetermined time before the completion of the processing presently executed thereby, and when two or more of said processors simultaneously output a common memory access request, common memory access permis­sion is granted to them in order of priority.

Claim 6

A bus control method for a system in which a plurality of digital signal processors are connected to a common memory which can be accessed by two or more processors in a time-division manner, wherein, when any of said processors needs to access said common memory, it outputs a common memory access request a predetermined time before the completion of the processing presently executed thereby, and when two or more of said processors simultaneously output a common memory access request, common memory access permis­sion is granted to them in order of priority.

Claim 7

An image processor having a plurality of unit processors each including a fetching unit for fetching input partial frame signals inputted to an input bus on a frame-by-frame basis, a processing unit for executing an encoding/decoding processing on the input partial frame signal fetched in the fetching unit, and an output unit for outputting the result of the coding/decoding processing in the processing unit, wherein the improvement comprises a storage unit for storing coded/decoded partial frame signals obtained as the result of said processing, a control unit for controlling said fetching, processing, storage and output operations in each of said unit processors, and a common storage unit for storing, when said coded/decoded partial frame signals are stored into said storage unit, a coded/decoded partial frame signal which is required to process a subsequent frame, said common storage unit being accessible from the relevant unit processor and at least one of the other unit processors.

Claim 8

An image processor having a plurality of unit processors each including a fetching unit for fetching input partial frame signals inputted to an input bus on a frame-by-frame basis, a processing unit for executing an encoding/decoding processing on the input partial frame signal fetched in the fetching unit, and an output unit for outputting the result of the coding/decoding processing in the processing unit, wherein the improvement comprises a storage unit for storing coded/decoded partial frame signals obtained as the result of said processing, a control unit for controlling said fetching, processing, storage and output operations in each of said unit processors, and a common storage unit for storing, when said coded/decoded partial frame signals are stored into said storage unit, a coded/decoded partial frame signal which is required to process a subsequent frame, said common storage unit being accessible from the relevant unit processor and at least one of the other unit processors.

Claim 9

An image processor having a plurality of unit processors which are respectively assigned specific frame regions of one picture frame to fetch input partial image signals corresponding to the specific frame regions, execute a signal processing on them and send the processed signals to an output bus, each unit processor being capable of fetching a signal processed by another unit processor, as being an input image auxiliary signal for neighbor process­ing, wherein each of said unit processors is assigned a plurality of frame regions which are not contiguous but separated from each other, and all said unit processors simultaneously start processing of input partial image signals and input image auxiliary signals after fetching the input partial image signals corresponding to the assigned frame regions.

Claim 10

An image processor having a plurality of unit processors which are respectively assigned specific frame regions of one picture frame to fetch input partial image signals corresponding to the specific frame regions, execute a signal processing on them and send the processed signals to an output bus, each unit processor being capable of fetching a signal processed by another unit processor, as being an input image auxiliary signal for neighbor process­ing, wherein each of said unit processors is assigned a plurality of frame regions which are not contiguous but separated from each other, and all said unit processors simultaneously start processing of input partial image signals and input image auxiliary signals after fetching the input partial image signals corresponding to the assigned frame regions.

Claim 11

An image processor according to Claim 5, wherein each of said unit processors has a storage unit for storing a signal processed therein, and the processed signal stored in said storage unit is read out to a common bus by a transfer control unit after completion of the signal processing operations in all said unit processors in such a manner that the readout signal can be fetched by another unit processor.