Embedded control technique for distributed control systems

Claim 2

An electronic system of the type having a plurality of functional elements comprising both intelligent elements (12, 13, 14; 24) and non-intelligent elements (34) interconnected by at least one time-division multiplexed data link (16, 18, 20, 22) for conveying information between the elements in time slots of said data link, characterized in that it comprises means for conveying messages between the elements in predetermined time slots of said data link, the messages being formatted to be readable by both types of elements so that only one control message format is required, whereby messages are transmitted transparently between elements over a data link used to convey information.

Claim 3

A system as claimed in claim 1, - wherein one (12, 13, 14) of the elements generates a message wherein the message includes command data and message control data, and inserts the message in a predetermined time slot of the data link, - wherein another (34) of the elements reads the message from the data link during the time slot, the message control data including an address of a register (38) or storage location in memory designated to receive the message on the receiving element (34), and - wherein the reading is performed by the receiving register (38).

Claim 4

A system as claimed in claim 2, - wherein the data link is a duplex data link (16, 18, 20, 22) having two paths for conveying information in two directions, - wherein said another (34) of the terminals generates a reply, inserts the reply in a predetermined time slot of the path of the data link (20, 22) that conveys information in a direction opposite from the path from which the message was read, and - wherein said one (12, 13, 14) of the elements reads the reply from the data link during the predetermined time slot in which the reply was inserted.

Claim 5

A system as claimed in claim 1, including intelligent elements (12, 13, 14; 24) having message-oriented control, and non-intelligent elements (34) having register-oriented control, wherein the message is generated in an intelligent control element (12, 13, 14), having a microprocessor (12) for controlling the system and for generating a plurality of control messages addressed to other system elements (24, 34).

Claim 6

A system as claimed in claim 4, - wherein the serial data link is a duplex serial data link (16, 18, 20, 22) having separate paths for conveying information in opposite directions between elements, - wherein the elements (24, 34) other than the intelligent control element (12, 13, 14) generate return messages and insert the return messages in predetermined time slots of a data link path to convey information to the intelligent control element (12, 13, 14) and wherein the return messages are read by the intelligent control element and stored in a number of shadow registers (13) which are included in the intelligent control element (12, 13, 14).

Claim 7

A system as claimed in claim 2, - wherein the message control data include a plurality of address bits for an address of an element or of a register of an element designated to receive the message, a message valid bit, an interrupt bit and a parity bit, wherein the valid bit, if set, indicates that a valid message is being sent in the time slot and that the time slot is not idle, and the interrupt bit, if set, indicates that the message is of an urgent nature and should be acted upon immediately, and wherein the addressed element only reads the message if the valid bit is set.

Claim 8

A system as claimed in claim 6, which includes intelligent elements (12, 13, 14; 24) each having a microprocessor (12, 28) adapted to receive message-oriented control, and non-intelligent elements (34), each having a register (38) adapted to receive register-oriented control, - wherein addressed intelligent elements (12, 13, 14; 24) interrupt said microprocessor (12, 28) to service said message only if the interrupt bit is set, and - wherein addressed non-intelligent register-oriented control elements (34) execute a read message immediately.

Claim 9

A distributed control communication system, comprising: - a control element (12, 13, 14) including a microprocessor (12) for generating system control messages; - at least one intelligent element (24) including a microprocessor (28) and a memory (30), and having message-oriented control; - at least one non-intelligent element (34) having register-oriented control: - a plurality of time-division multiplexed serial data links (16, 18, 20, 22) having first and second ends, each of the links being connected to one of the said system elements at a first end of the link; - switch means (10) connected to the second ends of the links, the time-division multiplexed serial data links and the switch means being operative to convey information between the system elements in time slots of the time-division multiplexed serial data links; and - means for conveying control messages from the control element (12, 13, 14) to designated ones of the elements and to convey return messages from the designated ones of the elements to the control element in predetermined time slots of the data links, the control messages being generated in a format with a plurality of bits and a length that fits within the time slots of the time-division multiplexed serial data links, the format being readable by both the intelligent elements and the non-intelligent elements.

Claim 10

A distributed control communication system, comprising: - a control element (12, 13, 14) including a microprocessor (12) for generating system control messages; - at least one intelligent element (24) including a microprocessor (28) and a memory (30), and having message-oriented control; - at least one non-intelligent element (34) having register-oriented control: - a plurality of time-division multiplexed serial data links (16, 18, 20, 22) having first and second ends, each of the links being connected to one of the said system elements at a first end of the link; - switch means (10) connected to the second ends of the links, the time-division multiplexed serial data links and the switch means being operative to convey information between the system elements in time slots of the time-division multiplexed serial data links; and - means for conveying control messages from the control element (12, 13, 14) to designated ones of the elements and to convey return messages from the designated ones of the elements to the control element in predetermined time slots of the data links, the control messages being generated in a format with a plurality of bits and a length that fits within the time slots of the time-division multiplexed serial data links, the format being readable by both the intelligent elements and the non-intelligent elements.

Claim 11

A system as claimed in claim 8, - wherein the serial links each comprise two separate paths for conveying information in opposite directions, and the means for conveying transmit messages from the control element on one path and transmit messages to the control element on the other path, - wherein the elements other than the control element (24, 34) generate return messages, insert the return messages in predetermined time slots of a path to convey information to the control element (12, 13, 14), and - wherein the control element (12, 13, 14) reads the return messages.

Claim 13

A system as claimed in claim 9, wherein the control element (12, 13, 14) includes a plurality of registers (13) into which the return messages are stored and the microprocessor (12) services the return messages in the registers in a routine manner.

Claim 14

A system as claimed in claim 10, wherein the address bits are set to an address of a register (38) in an non-intelligent element (34) or to a location in the memory (30) of an intelligent element (24).

Claim 15

A system as described in claim 10, wherein the microprocessor (28, 12) in an intelligent element (24) and in the control element (12, 13, 14) will interrupt to service a message received by the element if the message has the interrupt bit set.