EP0396940A2
Expired / Lapsed
EP
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Cache memory and related consistency protocol
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1990-04-18
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Granted: —
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Expires: 2010-04-18
Abstract
Abstract A cache memory for processors of a multiprocessor system provides data consistency in the system and avoids all unnecessary read operations in the working memory, except those required in case of miss on a read request, with a consistency protocol using five possible states of the cache data blocks (valid,invalid,reserved,modified,shared modified), inter-cache communication limited to bus watching of read/write operation in the system bus and buffer registers for performing off-line write operations through the system bus, including data block replacement operations.
Inventors
- 👤 Zulian Ferruccio
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 00:06
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
239 words
1) Cache memory for a processor associated thereto in a multiprocessor system, said cache memory being connected to a system bus for activation of read/write operations on said bus, comprising memory means(11) for storing a plurality of data blocks, a plurality of addresses each related to one of said data blocks and a plurality of state codes, each related to one of said data blocks, characterized in that: - each of said codes defines the status of the related block as Valid, Invalid, Reserved, Modified or Shared Modified, and in that said cache memory further comprises: - first logic means (13,26,17,34) for activating read operations on said system bus, only and exclusively in case of a data block read requested by said associated processor and related to a data block which is either missing from said cache memory or in invalid state, - second logic means (13,34,35,32) for activating on said system bus exclusively write operations if a write operation in a data block requested by said associated processor is related to a data block being either missing from said cache or present in a state other than reserved or modified, and - interface registers (25,27,28) coupled to said system bus and for storing a data block to be written through said system bus and the related address, so that said write operations on said system bus may be activated off-line as to said write request of said processor.
Claim 2
Dependent Claim
239 words
1) Cache memory for a processor associated thereto in a multiprocessor system, said cache memory being connected to a system bus for activation of read/write operations on said bus, comprising memory means(11) for storing a plurality of data blocks, a plurality of addresses each related to one of said data blocks and a plurality of state codes, each related to one of said data blocks, characterized in that: - each of said codes defines the status of the related block as Valid, Invalid, Reserved, Modified or Shared Modified, and in that said cache memory further comprises: - first logic means (13,26,17,34) for activating read operations on said system bus, only and exclusively in case of a data block read requested by said associated processor and related to a data block which is either missing from said cache memory or in invalid state, - second logic means (13,34,35,32) for activating on said system bus exclusively write operations if a write operation in a data block requested by said associated processor is related to a data block being either missing from said cache or present in a state other than reserved or modified, and - interface registers (25,27,28) coupled to said system bus and for storing a data block to be written through said system bus and the related address, so that said write operations on said system bus may be activated off-line as to said write request of said processor.
Claim 3
Dependent Claim
59 words
2) Cache memory as in claim 1, where said second logic means, at least in case of partial write requested by said associated processor and related to a data block which is either missing from said cache memory or present in invalid state, activates said write operation on said system bus without modifying the contents of said memory means.
Claim 4
Dependent Claim
62 words
3) Cache memory as in claim 1, where said second logic means, in case of a write requested by said associated processor and related to a data block in state shared modified, activates said write operation on said bus and modifies consistently the data of said block and the related binary code so as to define said block as in reserved state.
Claim 5
Dependent Claim
77 words
4) Cache memory as in claim 1 comprising second interface registers (25,26) interfacing with said system bus for latching a data block stored in said cache memory and the related address, said data block having to be saved due to a read operation activated on said system bus, so that the write operation to be activated on said system bus for saving said data block, can be performed in off-line mode and subsequently to said read operation.
Claim 6
Dependent Claim
70 words
5) Cache memory as in claim 4, comprising a comparator (36) for comparing an address present on said system bus and said address latched in one of said second interface registers and circuit means for receiving data present on said system bus and for modifying said data block latched in said second interface registers with the data present on said system bus, if said addresses compared by said comparator coincide.
References Cited (Backward Citations)
No citation records indexed.
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