EP0395835A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Improved cache accessing method and apparatus
Assignee: Intergraph Corp
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Filing: 1990-01-25
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Granted: —
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Expires: 2010-01-25
Abstract
Abstract An addressable cache memory stores a plurality of lines of data from the main memory, and a tag memory (typically a part of the cache memory) stores a corresponding plurality of real addresses associated with each line of data. A cache accessing unit receives a virtual address from a CPU. The virtual address comprises a real address portion and a virtual address portion, and the virtual address portion includes a virtual page and segment address. On each cache access, the cache accessing unit initially addresses the cache memory by concatenating the real address portion of the virtual address with an algorithmically determined first real address (i.e., a real page address). A translation memory translates the virtual address portion of the virtual address into a second real address as the cache memory is being accessed. A comparator compares the second real address with the first real address, and the data is retrieved from the cache memory when the first real address matches the second real address. All subsequent cache accesses are made using a combined address formed by concatenating the real address portion of the current virtual address to the previously translated real page address.
Inventors
- 👤 Howard Gene Sachs
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 08:12
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
218 words
In a computing system having a cache memory for storing data from a main memory, a cache memory management system comprising: an addressable cache memory for storing a plurality of lines of data forming a plurality of pages of data from a main memory, the cache memory including first real address storing means for storing a first real address associated with each page of data; address receiving means for receiving a virtual address from a CPU, the virtual address having a real address portion and a virtual address portion, the virtual address portion including a virtual page address; cache access means, coupled to the address receiving means, for addressing the cache memory with the real address portion of the virtual address; translation means, coupled to the address receiving means, for translating the virtual address portion of the virtual address into a second real address simultaneously with the accessing of the cache memory by the cache access means; and comparing means, coupled to the translation means and to the cache access means, for comparing the second real address with the first real address associated with the data addressed by the cache addressing means; wherein the cache access means includes data retrieving means for retrieving data from the cache memory when the first real address matches the second real address.
Claim 2
Dependent Claim
218 words
In a computing system having a cache memory for storing data from a main memory, a cache memory management system comprising: an addressable cache memory for storing a plurality of lines of data forming a plurality of pages of data from a main memory, the cache memory including first real address storing means for storing a first real address associated with each page of data; address receiving means for receiving a virtual address from a CPU, the virtual address having a real address portion and a virtual address portion, the virtual address portion including a virtual page address; cache access means, coupled to the address receiving means, for addressing the cache memory with the real address portion of the virtual address; translation means, coupled to the address receiving means, for translating the virtual address portion of the virtual address into a second real address simultaneously with the accessing of the cache memory by the cache access means; and comparing means, coupled to the translation means and to the cache access means, for comparing the second real address with the first real address associated with the data addressed by the cache addressing means; wherein the cache access means includes data retrieving means for retrieving data from the cache memory when the first real address matches the second real address.
Claim 3
Dependent Claim
23 words
The cache memory management system according to claim 1 wherein the cache accessing means addresses the cache memory with a real page address.
Claim 4
Dependent Claim
39 words
The cache memory management system according to claim 2 wherein the cache accessing means further comprises real page address predicting means for predicting a real page address, the predicted real page address being used for addressing the cache memory.
Claim 5
Dependent Claim
63 words
The cache memory management system according to claim 3 wherein the second real address includes a real page address, wherein the comparing means compares the real page address to the predicted real page address, and wherein the cache access means real readdresses the cache memory with the real page address when the real page address is unequal to the predicted real page address.
Claim 6
Dependent Claim
48 words
The cache memory management system according to claim 1 wherein the second real address includes a real page address, and wherein the cache access means addresses a page of data in the cache memory with the real address portion of the virtual address and the real page address.
Claim 7
Dependent Claim
39 words
The cache memory management system according to claim 1 wherein the second real address includes a real page address, and further comprising storing means, coupled to the translation means, for storing the real address provided by the translation means.
Claim 8
Dependent Claim
83 words
The cache memory management system according to claim 6 wherein the cache access means includes address combining means, coupled to the storing means and to the address receiving means, for providing a first combined address by combining a current real address portion of the virtual address with a real page address stored in the storing means and translated from a previous virtual address, and wherein the cache access means addresses a line of data in the cache memory with the first combined address.
Claim 9
Dependent Claim
58 words
The cache memory management system according to claim 7 wherein the comparing means includes page address comparing means, coupled to the translation means and to the storing means, for comparing the stored real page address to the real page address translated from the current virtual address when the first real address is unequal to the second real address.
Claim 10
Dependent Claim
52 words
The cache memory management system according to claim 8 wherein the combining means provides a second combined address by combining the real page address translated from the current virtual address with the real address portion of the current virtual address when the first real address in unequal to the second real address.
Claim 11
Dependent Claim
28 words
The cache memory management system according to claim 9 wherein the cache access means further comprises readdressing means for readdressing the cache memory with the second combined address.
Claim 12
Dependent Claim
56 words
The cache memory management system according to claim 10 further comprising main memory access means, coupled to the comparing means and to the main memory, for retrieving data from the main memory when the first real address is unequal to the second real address after the cache memory has been readdressed with the second combined address.
Claim 13
Independent Claim
155 words
A method for accessing data in a data processing system having a processing unit, a main memory and a cache memory for storing a plurality of pages of a plurality of lines of data comprising the steps of: storing a first real address associated with each page of data in the cache memory; receiving a virtual address from the processing unit, the virtual address having a real address portion and a virtual address portion, the virtual address portion including a virtual page address; addressing the cache memory with the real address portion of the virtual address; translating the virtual address portion of the virtual address into a second real address simultaneously with the addressing of the cache memory; comparing the second real address with the first real address associated with the page of data addressed in the cache; and retrieving data from the cache memory when the first real address matches the second real address.
Claim 14
Independent Claim
155 words
A method for accessing data in a data processing system having a processing unit, a main memory and a cache memory for storing a plurality of pages of a plurality of lines of data comprising the steps of: storing a first real address associated with each page of data in the cache memory; receiving a virtual address from the processing unit, the virtual address having a real address portion and a virtual address portion, the virtual address portion including a virtual page address; addressing the cache memory with the real address portion of the virtual address; translating the virtual address portion of the virtual address into a second real address simultaneously with the addressing of the cache memory; comparing the second real address with the first real address associated with the page of data addressed in the cache; and retrieving data from the cache memory when the first real address matches the second real address.
Claim 15
Dependent Claim
45 words
The method according to claim 12 wherein the second real address includes a real page address, and wherein the cache addressing step further comprises the step of addressing the cache memory with the real address portion of the virtual address and the real page address.
Claim 16
Dependent Claim
16 words
The method according to claim 13 further comprising the step of storing the real page address.
Claim 17
Dependent Claim
41 words
The method according to claim 14 wherein the cache addressing step further comprises the step of addressing the cache memory with the real address portion of a current virtual address and the real page address translated from a previous virtual address.
Claim 18
Dependent Claim
40 words
The method according to claim 15 further comprising the step of comparing the stored real page address to the real page address translated from a current virtual address when the first real address is unequal to the second real address.
Claim 19
Dependent Claim
67 words
The method according to claim 16 further comprising the step of readdressing the cache memory with the real address portion of the current virtual address and the real page address translated from the current virtual address when the first real address is unequal to the second real address and the stored real page address is unequal to the real page address translated from the current virtual address.
References Cited (Backward Citations)
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