Computer capable of expanding a memory capacity

Claim 2

A computer system capable of expanding a memory capacity, comprising: standard memory means (11) for storing data; a plurality of slot means (12, 13) into which a respective plurality of memory modules means (12M, 13M) for storing data may be inserted to expand said memory capacity; status line means (21, 31) connected to each of said plurality of slot means, for outputting a status signal including information which represents whether each respective memory module means is inserted into the slot means and which represents a memory capacity of the inserted memory module means when at least one of said plurality of memory module means is inserted into said plurality of slot means; designating means (15, 31, 32) connected to said status line means (21, 31), for outputting a signal which designates, in response to said status signals, an address range of said at least one memory module means inserted into said plurality of slot means; determining means (15, 34) responsive to the signal designating the address range from said designating means and an address signal for memory access for deter­mining whether said standard memory means or one of said plurality of memory module means inserted into the slot means is to be accessed; and execution means (14, 16 to 18) for accessing either one of said standard memory means or said one of said plurality of memory module means in accordance with a result of the determination of said determining means.

Claim 3

The computer system according to claim 1, characterized in that each of said plurality of memory module means comprises status means (TA, TB) which is connected to said status line means (21, 31) when the memory module means is inserted into respective one of said plurality of slot means and wherein said status means supplies to said status line means (21, 31) a sig­nal indicating that the memory module means is inserted into the respective slot means and indicating that a memory capacity of the memory module means.

Claim 4

The computer system according to claim 2, characterized in that said status means comprises a plu­rality of terminals connected to said status line means when the memory module means is inserted into the respective slot means, said plurality of terminals being preset to voltage values in accordance with the memory capacity of said memory module means.

Claim 5

The computer system according to claim 1, characterized in that said status line means comprises a plurality of signal lines arranged for each of said plu­rality of slot means.

Claim 6

The computer system according to claim 1, characterized in that said designating means includes a decoder (31) for decoding the status signal and an encoder (32) for outputting a signal designating a pre­determined address range in response to a signal output from said decoder.

Claim 7

The computer system according to claim 1, characterized in that said determining means includes a comparator (34) for comparing the address range desig­nated by the signal output from said encoder (32) with an address value designated by the address signal to determine one of the standard memory means (11) and the memory module means (12M, 13M) to be accessed and output a signal indicating a result of the determination.

Claim 8

The computer system according to claim 1, characterized in that said execution means comprises generation means for generating a memory control signal for controlling the memory access; means connected to said determining means and said generation means, for supplying the memory control signal to the memory to be accessed in accordance with the determination result of said determining means; and data transmission means for transmitting data read out from and data to be written in one of said standard memory means and said plurality of memory module means.

Claim 9

A memory control system characterized by comprising: a plurality of connecting means (12, 13) which may each be connected to respective plurality of memory means (12M, 13M) connected; first detecting means (15, 21, 31) for detecting whether said plurality of memory means is connected to a respective one of said plurality of connecting means; and setting means (14 to 18) connected to said first detecting means to receive address data, for setting a one of said memory means in an accessible state in response to a result of the detection of said first detection means and said address data.

Claim 10

A memory control system characterized by comprising: a plurality of connecting means (12, 13) which may each be connected to respective plurality of memory means (12M, 13M) connected; first detecting means (15, 21, 31) for detecting whether said plurality of memory means is connected to a respective one of said plurality of connecting means; and setting means (14 to 18) connected to said first detecting means to receive address data, for setting a one of said memory means in an accessible state in response to a result of the detection of said first detection means and said address data.

Claim 11

The memory control system according to claim 8, characterized in that said system further comprises second detecting means (15, 21, 31) for detecting a capacity of the any of said plurality of memory means connected to said connecting means, and said setting means (14 to 18) sets said one of said memory means in an accessible state in response to a result of the detection of said first and second detecting means and the address data.

Claim 12

The memory control system according to claim 9, characterized in that said setting means com­prises designating means (31, 32) for outputting a sig­nal which designates an address range of each of said plurality of memory means connected to said plurality of connecting means in response to a result of the detec­tion of said first and second detection means; determin­ing means (34) for determining which one of said plurality of memory means is designated by an address designated by the address data upon receiving the signal from said designating means (31, 32) and the address data; and setting means (14 to 18) for setting said one of said plurality of memory means in an accessible state in response to a result of the determination of said determining means.

Claim 13

A data processing system having a function of expanding a memory capacity, characterized by compris­ing: data processing means (22, 23) for instructing mem­ory access for data processing; standard memory means (11) connected to said data processing means, for storing data; a plurality of holding means (12, 13) each of which is detachably connected to a respective plurality of additional memory means, said additional memory means being added to said standard memory means and storing data to expand the memory capacity which is usable for said data processing means; detecting means (21, 31, 15) for detecting whether each of said holding means is connected to each of said plurality additional memory means and for, when at least one of said plurality of holding means is connected to at least one of said plurality of additional memory means, detecting a capacity of said at least one addi­tional memory means; determining means (14 to 18) for determining whether said standard memory means or one of said plu­rality of additional memory means is to be accessed, in response to a detection result of said detection means and the address data; and access means (10, 19, 23) connected to said data processing means, said standard memory means, and said plurality of additional memory means, for accessing either one of said standard memory means or at least one of said additional memory means memory means determined by said determining means in accordance with an instruc­tion of said data processing means.

Claim 14

A data processing system having a function of expanding a memory capacity, characterized by compris­ing: data processing means (22, 23) for instructing mem­ory access for data processing; standard memory means (11) connected to said data processing means, for storing data; a plurality of holding means (12, 13) each of which is detachably connected to a respective plurality of additional memory means, said additional memory means being added to said standard memory means and storing data to expand the memory capacity which is usable for said data processing means; detecting means (21, 31, 15) for detecting whether each of said holding means is connected to each of said plurality additional memory means and for, when at least one of said plurality of holding means is connected to at least one of said plurality of additional memory means, detecting a capacity of said at least one addi­tional memory means; determining means (14 to 18) for determining whether said standard memory means or one of said plu­rality of additional memory means is to be accessed, in response to a detection result of said detection means and the address data; and access means (10, 19, 23) connected to said data processing means, said standard memory means, and said plurality of additional memory means, for accessing either one of said standard memory means or at least one of said additional memory means memory means determined by said determining means in accordance with an instruc­tion of said data processing means.

Claim 15

The data processing system according to claim 11, characterized in that said detection means is connected to said holding means and comprises status line means (21, 31) for transmitting a status signal including information which represents whether any of plurality of said additional memory means is connected to each of said holding means and which represents a capacity of any said connected additional memory means connected to one of said holding means; and said deter­mining means comprises designating means (31, 32) for designating an address range of said plurality of addi­tional memory means connected to said holding means in accordance with a result of said detection means, speci­fying means (34) for comparing the address data and the address range designated by said designating means to specify either one of said standard memory means or at least one of said additional memory means to be accessed, and access means (14, 16 to 18) for allowing said specified memory means specified by said specifying means to be accessed.

Claim 16

The data processing system according to claim 11, characterized in that said additional memory means comprises status means (TA, TB) connected to said status line means, for supplying the status signal to said status line means.

Claim 17

The data processing system according to claim 11, characterized in that said designating means includes a decoder (31) for decoding the status signal and an encoder (32) for outputting a signal designating a predetermined address range in response to a signal output from said decoder.

Claim 18

A memory control system characterized by comprising: a connecting means (12, 13) to which a memory means (12M, 13M), having a variable memory capacity, for stor­ing data may be detachably connected; first detecting means (15, 21, 31) for detecting whether the memory means is connected to the connecting means; second detecting means for detecting a memory capacity of the memory means when the memory means is connected to the connecting means; and setting means (14 to 18) connected to the first and second detecting means and receiving address data, for setting the memory means in an accessible state in response to a result of the detection of the first and second detection means and the address data.

Claim 19

A memory control system characterized by comprising: a connecting means (12, 13) to which a memory means (12M, 13M), having a variable memory capacity, for stor­ing data may be detachably connected; first detecting means (15, 21, 31) for detecting whether the memory means is connected to the connecting means; second detecting means for detecting a memory capacity of the memory means when the memory means is connected to the connecting means; and setting means (14 to 18) connected to the first and second detecting means and receiving address data, for setting the memory means in an accessible state in response to a result of the detection of the first and second detection means and the address data.