EP0391584A2
Expired / Lapsed
EP
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Fifo memory system
Assignee: NCR International Inc
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Filing: 1990-03-23
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Granted: —
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Expires: 2010-03-23
Abstract
Abstract A FIFO memory system for buffering data between two data buses includes a RAM memory (12), write and read pointer registers (14, 16), an offset generator (16), a programmable offset register (20), and a comparator (22). The write pointer register (14) stores the address of the next data element to be written into the RAM memory (12), and the read pointer register stores (16) the address of the next data element to be read from the RAM memory (12). The offset generator (18) compares the contents of the registers (14, 16), and generates at an output thereof an offset signal representing the amount of memory space occupied. The programmable offset register (20) provides a programmed offset signal. The comparator (22) compares the offset signal and the programmed offset signal, and provides a ready signal when the offset signal is greater than or equal to the programmed offset signal. In one embodiment, the addresses stored in the write and read pointer registers (14, 16) are encoded in a minimum change code such as Gray code.
Inventors
- 👤 David L. Simpson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 10:42
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F5/12; G06F5/14; G06F2205/00; G06F2205/10; G06F2205/102; G06F2205/12; G06F2205/126
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
143 words
A FIFO memory system, including a RAM memory (12), write pointer register means (14) adapted to store the address of the next data element to be written into said RAM memory (12), and read pointer register means (16) adapted to store the address of the next data element to be read from said RAM memory (16), characterized by offset generator means (18) adapted to compare the contents of said write and read pointer register means (14, 16) and to generate an output signal (OFF) representing the amount of memory space occupied, programmable offset register means (20) adapted to provide a programmable offset signal (POFF), and comparator means (22) adapted to compare said offset signal (OFF) and said programmed offset signal (POFF) and to provide an output signal (READY) when said offset signal is greater than or equal to said programmed offset signal (POFF).
Claim 2
Dependent Claim
143 words
A FIFO memory system, including a RAM memory (12), write pointer register means (14) adapted to store the address of the next data element to be written into said RAM memory (12), and read pointer register means (16) adapted to store the address of the next data element to be read from said RAM memory (16), characterized by offset generator means (18) adapted to compare the contents of said write and read pointer register means (14, 16) and to generate an output signal (OFF) representing the amount of memory space occupied, programmable offset register means (20) adapted to provide a programmable offset signal (POFF), and comparator means (22) adapted to compare said offset signal (OFF) and said programmed offset signal (POFF) and to provide an output signal (READY) when said offset signal is greater than or equal to said programmed offset signal (POFF).
Claim 3
Dependent Claim
145 words
A FIFO memory system according to 1, characterized in that said comparator means (22) includes: a wrap around detector (26) adapted to receive said offset signal, to monitor changes in said offset signal determining if the RAM memory (12) is full or empty when said offset is zero, and to generate at an output thereof a wrap signal indicating full or empty; a comparison circuit (28) adapted to receive said offset signal (OFF) and said programmed offset signal (POFF) to determine when said offset signal (OFF) is greater than or equal to said programmed offset signal (POFF), and to generate at an output thereof a greater than or equal to signal (GE/); and a flag generator circuit (30) connected to the outputs of said wrap around detector (26), said comparison circuit (28), and said offset generator (18) and adapted to provide said output signal (READY).
Claim 4
Dependent Claim
145 words
A FIFO memory system according to 1, characterized in that said comparator means (22) includes: a wrap around detector (26) adapted to receive said offset signal, to monitor changes in said offset signal determining if the RAM memory (12) is full or empty when said offset is zero, and to generate at an output thereof a wrap signal indicating full or empty; a comparison circuit (28) adapted to receive said offset signal (OFF) and said programmed offset signal (POFF) to determine when said offset signal (OFF) is greater than or equal to said programmed offset signal (POFF), and to generate at an output thereof a greater than or equal to signal (GE/); and a flag generator circuit (30) connected to the outputs of said wrap around detector (26), said comparison circuit (28), and said offset generator (18) and adapted to provide said output signal (READY).
Claim 5
Dependent Claim
39 words
A FIFO memory system according to claim 2, characterized in that said flag generator circuit (30) is further adapted to provide a full or empty signal (FULL/; EMPTY/), indicating that said RAM memory (12) is full or empty, respectively.
Claim 6
Dependent Claim
83 words
A FIFO memory system according to claim 3, characterized in that said write pointer register means (14) is adapted to store a minimum change coded address of said next data element to be written and said read pointer register means (16) is adapted to store a minimum change coded address of said next data element to be read, and in that said system includes a binary to minimum change code coverter (14) connecting said offset register means (20) to said comparator means (22).
Claim 7
Dependent Claim
108 words
A FIFO memory system according to claim 4, characterized in that said wrap around detector (26) includes a NAND gate (158) and a D-type flip-flop (156) having D and CK input ports and a Q output port, wherein said D input port is connected to a single data bit line from the output of said offset generator means (18) the inputs to said NAND gate (158) are connected to a plurality of other data bit lines from the output of said offset generator means (158), the output of said NAND gate (158) is connected to said CK input port, and said Q output port provides said wrap signal.
Claim 8
Dependent Claim
67 words
A FIFO memory system according to claim 2, characterized in that said flag generator circuit (30) includes an AND gate (78) and a NOR gate (82) said AND gate (78) receiving as inputs the inverse of said wrap and offset signals, said NOR gate (82) receives as inputs the output of said AND gate (78) and the inverse of said greater than or equal to signal (GE/).
Claim 9
Dependent Claim
161 words
A FIFO memory system according to claim 1, characterized in that said write pointer register means (14) includes first incrementing means adapted to increment said write point register means (14) in response to a write signal received thereby, and said read pointer register means (16) includes second incrementing means adapted to increment said read pointer register means (16) in response to a read signal recieved thereby, in that said write signal has a leading and trailing edge and said first incrementing means is responsive to said trailing edge, and said RAM memory (12) has means for writing data into said RAM memory (12) in response to the leading edge of said write signal, and in that said read signal has a leading and trailing edge and said second incrementing means is responsive to said trailing edge, and said RAM memory (12) has means for reading data from said RAM memory (12) in response to the leading edge of said read signal.
Claim 10
Dependent Claim
72 words
FIFO memory system according to claim 1, characterized in that said programmable offset register means (20) includes loading means adapted to load said register means (20) with said programmed offset signal, in that said RAM memory (12) has an input data bus (36) adapted to write data to said memory (12), and in that said loading means includes a connection (44) between said bus (36) and said programmable offset register means (20).
Claim 11
Dependent Claim
39 words
A FIFO memory system according to claim 1, characterized in that said RAM memory (12) is a dual ported RAM having input and output data buses for writing data to and reading data from, respectively, said RAM memory (12).
Claim 12
Independent Claim
117 words
A method for buffering data between two data buses, characterized by the steps of: loading a programmable offset register (20) with a programmed offset value (POFF); writing a data element into a RAM memory (12); incrementing a write pointer register (14) to identify the address of the next data element to be written into said RAM memory (12); comparing the contents of said write and read pointer registers and generating an offset value (OFF) therefrom; comparing said offset value (OFF) with said programmed offset value (POFF); and generating a ready signal indicating said RAM memory (12) is ready to be read when said offset value (OFF) is greater than or equal to said programmed offset value (POFF).
Claim 13
Independent Claim
117 words
A method for buffering data between two data buses, characterized by the steps of: loading a programmable offset register (20) with a programmed offset value (POFF); writing a data element into a RAM memory (12); incrementing a write pointer register (14) to identify the address of the next data element to be written into said RAM memory (12); comparing the contents of said write and read pointer registers and generating an offset value (OFF) therefrom; comparing said offset value (OFF) with said programmed offset value (POFF); and generating a ready signal indicating said RAM memory (12) is ready to be read when said offset value (OFF) is greater than or equal to said programmed offset value (POFF).
Claim 14
Dependent Claim
43 words
A method according to claim 10, characterized in that said step of comparing the contents of said write and read pointer registers (14, 16) includes the step of subtracting the contents of said pointer registers (14, 16) thereby generating said offset value (OFF).
Claim 15
Dependent Claim
74 words
A method according to claim 10 characterized in that said step of comparing said offset value (OFF) with said programmed offset value (POFF) includes the steps of: monitoring changes in said offset vlaue (OFF); determining if said RAM memory (12) is full or empty when the offset value is zero; and generating a full or empty signal indicating that said RAM memory (12) is full or empty, respectively, when the offset value is zero.
Claim 16
Independent Claim
33 words
A method according to any one of claims 10 to 12, characterized in that said write and read pointer registers (14, 16) are adapted to store memory addresses in minimum change coded form.
References Cited (Backward Citations)
No citation records indexed.
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