MOS-pilot structure for an insulated gate transistor and method of providing a pilot current in such a transistor

Claim 2

A semiconductor device, comprising: an anode region of a first conductivity type semiconductor material; anode means for electrically connecting said anode region to a first terminal of said device; a drift region, of a second conductivity type semiconductor material, having a first surface contacting said anode region and a second surface opposite to said first surface; a base region, of said first conductivity type semiconductor material, formed in said drift region second surface and having separated first and second boundary portions each adjacent to both said drift region and said second surface; at least one emitter region, of said second conductivity type semiconductor material, formed in a first portion of said base region adjacent to said first base region boundary portion and on an opposite side thereof from said drift region; cathode means for electrically connecting all of said at least one emitter region and said base region to a second terminal of said device; a gate electrode insulatively overlying both of said base region boundary portions and an adjacent portion of said drift region, and operative to cause a channel current to flow through said first base region boundary portion and between said anode and cathode means, responsive to application of a bias potential between said cathode means and a gate terminal of said device, connected to said gate electrode;

Claim 3

A semiconductor device, comprising: an anode region of a first conductivity type semiconductor material; anode means for electrically connecting said anode region to a first terminal of said device; a drift region, of a second conductivity type semiconductor material, having a first surface contacting said anode region and a second surface opposite to said first surface; at least first and second base regions, of said first conductivity type semiconductor material, formed in said drift region second surface and having respective first and second boundary portions each adjacent to both said drift region and said second surface; at least one emitter region, of said second conductivity type semiconductor material, formed in said first base region adjacent to said first base region boundary portion and on an opposite side thereof from said drift region; cathode means for electrically connecting said at least one emitter region and said first base region to a second terminal of said device; a gate electrode insulatively overlying both of said base region boundary portions and an adjacent portion of said drift region, and operative to cause a channel current to flow through said first base region boundary portion and between said anode and cathode means, responsive to application of a bias potential between said cathode means and a gate terminal of said device, connected to said gate electrode; at least one pilot emitter region, of said second conductivity type semiconductor material, formed in said second base region, adjacent to said second base region boundary portion and on an opposite side thereof from said drift region; and pilot means for connecting said at least one pilot emitter region to a third terminal of said device to provide a pilot current flowing through said third terminal and having a magnitude substantially equal to a fixed proportion of the channel current then flowing.

Claim 4

A semiconductor device, comprising: an anode region of a first conductivity type semiconductor material; anode means for electrically connecting said anode region to a first terminal of said device; a drift region, of a second conductivity type semiconductor material, having a first surface contacting said anode region and a second surface opposite to said first surface; at least first and second base regions, of said first conductivity type semiconductor material, formed in said drift region second surface and having respective first and second boundary portions each adjacent to both said drift region and said second surface; at least one emitter region, of said second conductivity type semiconductor material, formed in said first base region adjacent to said first base region boundary portion and on an opposite side thereof from said drift region; cathode means for electrically connecting said at least one emitter region and said first base region to a second terminal of said device; a gate electrode insulatively overlying both of said base region boundary portions and an adjacent portion of said drift region, and operative to cause a channel current to flow through said first base region boundary portion and between said anode and cathode means, responsive to application of a bias potential between said cathode means and a gate terminal of said device, connected to said gate electrode; at least one pilot emitter region, of said second conductivity type semiconductor material, formed in said second base region, adjacent to said second base region boundary portion and on an opposite side thereof from said drift region; and pilot means for connecting said at least one pilot emitter region to a third terminal of said device to provide a pilot current flowing through said third terminal and having a magnitude substantially equal to a fixed proportion of the channel current then flowing.

Claim 5

A semiconductor device formed of a multiplicity of cells interconnected in a lattice structure, comprising: a common anode region of a first conductivity type semiconductor material; common anode means for electrically connecting said anode region to a first terminal of said device; a common drift region, of a second conductivity type semiconductor material, having a first surface contact­ing said anode region and a second surface opposite to said first surface; a common base region, of said first conductivity type semiconductor material, formed in said drift region second surface and having a multiplicity of openings there­in, with each opening occupied by an intermediate portion of said drift region and with each opening bounded by a base region boundary portion and defining one of said multiplic­ity of cells; a first plurality of said multiplicity of cells, each including: (a) a different one of said drift region interme­diate portions, (b) at least one emitter region, of said second conductivity type semiconductor material, formed in a first portion of said base region spaced from an associated different one of said intermediate portions by a first section of an associated different one of said base region boundary portions, (c) cathode means for electrically connecting said at least one emitter region and the adjacent base region of each of said first plurality of cells to a second terminal of said device, (d) a gate electrode insulatively overlying both of the associated base region boundary portion and at least a part of the different intermediate drift region portion of each of said first plurality of cells, and operative to cause a channel current to flow through said first section of said associated base region boundary portion and between said common anode and cathode means, responsive to application of a bias potential between said cathode means and a gate terminal of said device, connected to said gate electrode, and (e) at least one pilot emitter region, of said second conductivity type semiconductor material, formed in a second portion of said base region, different from said base region first portion, and spaced from the associated different one of said drift region intermedi­ate portions by a second section of said associated base region boundary portion interposed therebetween; and pilot means for connecting said at least one pilot emitter region of each of a selected number of said first plurality of cells to a third terminal of said device, to provide a pilot current flowing through said third terminal and having a magnitude substantially equal to a fixed proportion of the channel currents then flowing in said first plurality of cells.

Claim 6

A semiconductor device formed of a multiplicity of cells interconnected in a lattice structure, comprising: a common anode region of a first conductivity type semiconductor material; common anode means for electrically connecting said anode region to a first terminal of said device; a common drift region, of a second conductivity type semiconductor material, having a first surface contact­ing said anode region and a second surface opposite to said first surface; a common base region, of said first conductivity type semiconductor material, formed in said drift region second surface and having a multiplicity of openings there­in, with each opening occupied by an intermediate portion of said drift region and with each opening bounded by a base region boundary portion and defining one of said multiplic­ity of cells; a first plurality of said multiplicity of cells, each including: (a) a different one of said drift region interme­diate portions, (b) at least one emitter region, of said second conductivity type semiconductor material, formed in a first portion of said base region spaced from an associated different one of said intermediate portions by a first section of an associated different one of said base region boundary portions, (c) cathode means for electrically connecting said at least one emitter region and the adjacent base region of each of said first plurality of cells to a second terminal of said device, (d) a gate electrode insulatively overlying both of the associated base region boundary portion and at least a part of the different intermediate drift region portion of each of said first plurality of cells, and operative to cause a channel current to flow through said first section of said associated base region boundary portion and between said common anode and cathode means, responsive to application of a bias potential between said cathode means and a gate terminal of said device, connected to said gate electrode, and (e) at least one pilot emitter region, of said second conductivity type semiconductor material, formed in a second portion of said base region, different from said base region first portion, and spaced from the associated different one of said drift region intermedi­ate portions by a second section of said associated base region boundary portion interposed therebetween; and pilot means for connecting said at least one pilot emitter region of each of a selected number of said first plurality of cells to a third terminal of said device, to provide a pilot current flowing through said third terminal and having a magnitude substantially equal to a fixed proportion of the channel currents then flowing in said first plurality of cells.

Claim 7

4 . The device of claim 3, further comprising a second plurality of said multiplicity of cells, different from said first plurality, each including: a different one of said drift region intermediate portions; at least one emitter region, of said second conductivity type semiconductor material, formed in said base region and spaced from an associated different one of said intermediate portions by an associated different one of said base region boundary portions; said cathode means also electrically connecting all of said at least one emitter region and the adjacent base region of each of said second plurality of cells to said second terminal; and a gate electrode, insulatively overlying both of at least a part of the different intermediate drift region portion and the associated base region boundary portion of each of said second plurality of cells, connected to said gate terminal and operative to cause another channel current to flow through said associated base region boundary por­tion, responsive to application of said bias potential between said gate terminal and said cathode means; and said pilot means providing said pilot current with a magnitude substantially equal to a fixed proportion of the sum of all channel currents then flowing in said first and second plurality of cells.

Claim 8

A semiconductor device formed of a multiplicity of cells interconnected in a lattice structure, comprising: a common anode region of a first conductivity type semiconductor material; common anode means for electrically connecting said anode region to a first terminal of said device; a common drift region, of a second conductivity type semiconductor material, having a first surface contact­ing said anode region and a second surface opposite to said first surface; a plurality of base regions, of said first con­ductivity type semiconductor material, formed in said drift region second surface and having a multiplicity of openings therebetween, with each opening occupied by an intermediate portion of said drift region and with each drift region intermediate portion bounded by a plurality of associated base region boundary portions and defining one of said multiplicity of cells; a first plurality of said multiplicity of cells, each including: (a) a different one of said drift region interme­diate portions, (b) at least one emitter region, of said second conductivity type semiconductor material, formed in one base region of said plurality of base regions and spaced from an associated different one of said plurality of associated intermediate portions by an associated different one of said plurality of associated base region boundary portions, (c) cathode means for electrically connecting said at least one emitter region and said one base region of each of said first plurality of cells to a second terminal of said device, (d) a gate electrode, insulatively overlying both of at least a part of the different interme­diate drift region portion and the plurality of associated base region boundary portions of each of said first plurality of cells, and operative to cause a channel current to flow through said associated base region boundary portions and between said common anode and cathode means, responsive to application of a bias potential between said cathode means and a gate terminal of said device, connected to said gate electrode, and (e) at least one pilot emitter region, of said second conductivity type semiconductor material, formed in another one of said plurality of base regions, and spaced from the associated different one of said drift region intermediate portions by another one of said plurality of associated base region boundary portions interposed therebetween; and pilot means for connecting said at least one pilot emitter region of each of a selected number of said first plurality of cells to a third terminal of said device, to provide a pilot current flowing through said third terminal and having a magnitude substantially egual to a fixed proportion of the channel currents then flowing in said first plurality of cells.

Claim 9

A semiconductor device formed of a multiplicity of cells interconnected in a lattice structure, comprising: a common anode region of a first conductivity type semiconductor material; common anode means for electrically connecting said anode region to a first terminal of said device; a common drift region, of a second conductivity type semiconductor material, having a first surface contact­ing said anode region and a second surface opposite to said first surface; a plurality of base regions, of said first con­ductivity type semiconductor material, formed in said drift region second surface and having a multiplicity of openings therebetween, with each opening occupied by an intermediate portion of said drift region and with each drift region intermediate portion bounded by a plurality of associated base region boundary portions and defining one of said multiplicity of cells; a first plurality of said multiplicity of cells, each including: (a) a different one of said drift region interme­diate portions, (b) at least one emitter region, of said second conductivity type semiconductor material, formed in one base region of said plurality of base regions and spaced from an associated different one of said plurality of associated intermediate portions by an associated different one of said plurality of associated base region boundary portions, (c) cathode means for electrically connecting said at least one emitter region and said one base region of each of said first plurality of cells to a second terminal of said device, (d) a gate electrode, insulatively overlying both of at least a part of the different interme­diate drift region portion and the plurality of associated base region boundary portions of each of said first plurality of cells, and operative to cause a channel current to flow through said associated base region boundary portions and between said common anode and cathode means, responsive to application of a bias potential between said cathode means and a gate terminal of said device, connected to said gate electrode, and (e) at least one pilot emitter region, of said second conductivity type semiconductor material, formed in another one of said plurality of base regions, and spaced from the associated different one of said drift region intermediate portions by another one of said plurality of associated base region boundary portions interposed therebetween; and pilot means for connecting said at least one pilot emitter region of each of a selected number of said first plurality of cells to a third terminal of said device, to provide a pilot current flowing through said third terminal and having a magnitude substantially egual to a fixed proportion of the channel currents then flowing in said first plurality of cells.

Claim 10

The device of claim 5, further comprising a second plurality of said multiplicity of cells, different from said first plurality, each including: a different one of said drift region intermediate portions; at least one emitter region, of said second conductivity type semiconductor material, formed in a further one of said plurality of base regions and spaced from an associated different one of said intermediate portions by an associated different one of said plurality of base region boundary portions; said cathode means also electrically connecting said at least one emitter region and said further one base region of each of said second plurality of cells to said second terminal; and a gate electrode, insulatively overlying both of at least a part of the different intermediate drift region portion and the plurality of associated base region boundary portions of each of said second plurality of cells, connected to said gate terminal and operative to cause another channel current to flow through said plurality of associated base region boundary portions, responsive to application of said bias potential between said gate terminal and said cathode means; and said pilot means providing said pilot current with a magnitude substantially egual to a fixed proportion of the sum of all channel currents then flowing in said first and second plurality of cells.

Claim 12

The device of Claim 1 or 2, wherein said pilot means is electrically connected only to said at least one pilot emitter region.

Claim 13

The device of Claim 1 or 2, wherein said pilot means comprises a pilot emitter electrode to electrically connect said at least one pilot emitter region to a sense resistor to produce a sense voltage across said resistor, responsive to said pilot current flowing through said resistor.

Claim 14

The device of Claim 3, 4, 5 or 6, wherein said pilot means is electrically connected only to said at least one pilot emitter region of each of said first plurality of cells.

Claim 15

The device of Claim 3, 4, 5 or 6, wherein said pilot means comprises a pilot emitter electrode to electrically connect said at least one pilot emitter region of each selected one of the first plurality of cells to a sense resistor to produce a sense voltage across said resistor, responsive to said pilot current flowing through said resistor.

Claim 18

The method of claim 12, further comprising the step of producing a sense voltage responsive to the pilot current flowing through the second device terminal.

Claim 19

The method of claim 12, wherein the semiconductor device has a multiplicity of IGT cells interconnected in rows and columns, defining a lattice structure, with each cell normally having a gate electrode and a plurality of associated gate bridges interconnecting the gate electrodes of adjacent cells, said method further comprising the steps of: substituting a conductive contact strip for a selected number of the gate electrodes and associated gate bridges of a selected one of a gateless column and a gate­less row of the lattice structure; the designating step includes the step of select­ing at least one cell proximate to the selected one of the gateless column and the gateless row; and the connecting step includes connecting the contact metal strip only between each designated pilot emitter region and the second terminal of the device.