EP0386804A2
Expired / Lapsed
EP
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Arrangement for measuring a quiescent current of an integrated monolithic digital circuit, integrated monolithic digital circuit provided with such an arrangement and testing apparatus provided with such an arrangement
Assignee: Koninklijke Philips NV
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Filing: 1990-01-04
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Granted: —
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Expires: 2010-01-04
Abstract
Abstract An arrangement is proposed for measuring a quiescent current of a digital IC. The arrangement comprises a current sensor in series with the IC and the supply, voltage stabilization means for stabilizing the voltage across the IC and signal processing means coupled thereto for processing the measured quiescent current. The quiescent current is measured when no flip-flops are switched in the IC. By means of the arrangement, there can be measured rapidly and accurately whether the quiescent current assumes an abnormal value, which indicates that the IC exhibits defects. The signal processing means comprise a current mirror, which is coupled to a current comparator circuit supplying a digital output signal for determining a defect.
Inventors
- 👤 Sebastiaan Constant Verhelst
- 👤 Evert Seevinck
- 👤 Keith Baker
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 13:44
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G01R31/3004; G01R19/00; G01R19/145; G01R19/15
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
91 words
An arrangement for measuring a quiescent current of an integrated monolithic digital circuit, which arrangement comprises a transistor as current sensor for measuring the quiescent current, which is provided with a first connection terminal for coupling to a supply terminal of the integrated monolithic circuit and with a second connection terminal for coupling to a supply, characterized in that the arrangement comprises voltage stabilization means for stabilizing a voltage at the first connection terminal and signal processing means coupled to the voltage stabilization means for signal processing of the quiescent current.
Claim 2
Dependent Claim
91 words
An arrangement for measuring a quiescent current of an integrated monolithic digital circuit, which arrangement comprises a transistor as current sensor for measuring the quiescent current, which is provided with a first connection terminal for coupling to a supply terminal of the integrated monolithic circuit and with a second connection terminal for coupling to a supply, characterized in that the arrangement comprises voltage stabilization means for stabilizing a voltage at the first connection terminal and signal processing means coupled to the voltage stabilization means for signal processing of the quiescent current.
Claim 3
Dependent Claim
64 words
An arrangement as claimed in Claim 1, characterized in that the voltage stabilization means comprise a differential amplifier, of which a first input is coupled to the first input terminal, a second input is coupled to the second connection terminal or to a connection terminal for connection to a reference voltage source and an output is coupled to a gate electrode of a transistor.
Claim 4
Dependent Claim
53 words
An arrangement as claimed in Claim 1 or 2, characterized in that the output of the differential amplifier is coupled to the gate electrode via a modification circuit for modifying the operation of the current sensor outside a quiescent current measuring period or outside a quiescent current measurement of the integrated monolithic circuit.
Claim 5
Dependent Claim
27 words
An arrangement as claimed in Claim 3, characterized in that the modification means that the current sensor in the form of a transistor is made fully conducting.
Claim 6
Dependent Claim
62 words
An arrangement as claimed in Claim 1, 2, 3 or 4, characterized in that the signal processing means comprise a first transistor, which constitutes with the current sensor in the form of a transistor a current mirror configuration, which is designed to supply via an output electrode of the first transistor a current, which is a current image of the quiescent current.
Claim 7
Dependent Claim
89 words
An arrangement as claimed in Claim 5, characterized in that the signal processing means comprise a differential amplifier, which is coupled through a first input to the first input terminal, through a second input to the output electrode of the first transistor and through an output to a gate electrode of a second transistor, which second transistor is coupled through a first output electrode to the output electrode of the first transistor, while a second output electrode of this second transistor serves to supply a further processed quiescent current.
Claim 8
Dependent Claim
48 words
An arrangement as claimed in Claim 5 or 6, characterized in that the signal processing means comprise further transistors, which constitute with the current sensor a current mirror configuration, while for obtaining the different processed quiescent currents the transistors of the signal processing means have different geometric dimensions.
Claim 9
Dependent Claim
56 words
An arrangement as claimed in any one of the preceding Claims, characterized in that the arrangement comprises comparison means coupled to the signal processing means for comparing the processed quiescent current with at least one reference current or reference voltage, the comparison means being designed to indicate when the reference current or reference voltage is exceeded.
Claim 10
Dependent Claim
67 words
An arrangement as claimed in Claim 8, characterized in that the comparison means comprise at least one current mirror configuration having a first input for the supply of a processed quiescent current, a second input for the supply of a reference voltage and a digital output assuming in dependence upon the processed quiescent currents with respect to the reference currents a first and a second value, respectively.
Claim 11
Dependent Claim
20 words
An arrangement as claimed in Claim 8, characterized in that the comparison means are constituted by analogue voltage comparison means.
Claim 12
Dependent Claim
25 words
An arrangement as claimed in Claim 8, 9 or 10, characterized in that an output of the comparison means is coupled to a scan chain.
Claim 13
Dependent Claim
25 words
An arrangement as claimed in Claim 8, 9 or 10, characterized in that the output of the comparison means is coupled to a self-test circuit.
Claim 14
Dependent Claim
52 words
An integrated monolithic digital circuit comprising at least one subcircuit, characterized in that the integrated monolithic circuit comprises at least one arrangement or at least a part thereof as claimed in any one of the preceding Claims for measuring the quiescent current of subcircuits, of combinations of subcircuits or of all subcircuits.
Claim 15
Dependent Claim
50 words
An integrated monolithic digital circuit comprising an arrangement as claimed in any one of Claims 1 to 10 and a boundary scan logic circuit for testing integrated circuits on printed circuit boards, in which the quiescent current measuring arrangement and the boundary scan logic circuit are coupled to each other.
Claim 16
Dependent Claim
38 words
A testing apparatus for measuring a quiescent current of an integrated monolithic digital circuit, characterized in that the testing apparatus comprises at least a part of the arrangement as claimed in any one of Claims 1 to 10.
References Cited (Backward Citations)
No citation records indexed.
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