EP0386631A2
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EP
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Eprom memory with crosspoint configuration and method for its manufacture
Assignee: STMicroelectronics SRL
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Filing: 1990-03-01
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Granted: —
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Expires: 2010-03-01
Abstract
Abstract In order to obtain an EPROM memory array with high compactness and the possibility of asymmetrically doping the channel, an array is proposed which comprises a substrate (1) having a first conductivity type, first and second bit lines (2,3) having the opposite conductivity type and extending parallel and mutually alternated in the substrate, a plurality of thick insulating material regions (4) extending at least partially in the substrate above and parallel to the first bit lines (2), a plurality of floating gate regions (5) extending above the substrate perpendicular to and between adjacent pairs of bit lines (2,3), a plurality of word lines (7) extending perpendicular to the bit lines and above, but electrically insulated from, the floating gate regions (5), wherein the second bit lines (3) extend up to the surface of the substrate and define unburied bit lines to the side whereof it is possible to provide enriched channel regions (13). The unburied bit lines (3) can furthermore be subjected to a siliciding process to reduce series resistance.
Inventors
- 👤 Orio Bellezza
- 👤 Massimo Melanotte
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 22:54
CPC Classifications
H; H10; H10B; H10B41/00; H10B69/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
174 words
An EPROM memory array with crosspoint configuration, comprising a semiconductor material body (1) with a first conductivity type defining a main surface (18), a plurality of source and drain (2,3) regions with a second conductivity type opposite to the first conductivity type, said source and drain regions extending alternately and parallel to one another in said semiconductor material body, said plurality of source and drain regions defining first and second bit lines (2,3), a plurality of insulation material regions (4) extending at least partially in said semiconductor material body (1) above said first bit lines (2) and parallel to said bit lines (2,3), a plurality of floating gate regions (5) extending above said semiconductor material body (1) perpendicular to said bit lines between adjacent pairs of bit lines (2,3), a plurality of word lines (7) extending perpendicular to said bit lines (2,3) and above but electrically insulated from said floating gate regions (5), characterized in that said second bit lines (3) extend up to said main surface (18) of said semiconductor material body (1).
Claim 2
Dependent Claim
174 words
An EPROM memory array with crosspoint configuration, comprising a semiconductor material body (1) with a first conductivity type defining a main surface (18), a plurality of source and drain (2,3) regions with a second conductivity type opposite to the first conductivity type, said source and drain regions extending alternately and parallel to one another in said semiconductor material body, said plurality of source and drain regions defining first and second bit lines (2,3), a plurality of insulation material regions (4) extending at least partially in said semiconductor material body (1) above said first bit lines (2) and parallel to said bit lines (2,3), a plurality of floating gate regions (5) extending above said semiconductor material body (1) perpendicular to said bit lines between adjacent pairs of bit lines (2,3), a plurality of word lines (7) extending perpendicular to said bit lines (2,3) and above but electrically insulated from said floating gate regions (5), characterized in that said second bit lines (3) extend up to said main surface (18) of said semiconductor material body (1).
Claim 3
Dependent Claim
57 words
An array according to claim 1, characterized by a plurality of enriched regions (13) of said first conductivity type but with a higher level of doping impurities than said semiconductor material body (1), said enriched regions (13) extending parallel to said second bit lines (3), between said second bit lines (3) and said semiconductor material body (1).
Claim 4
Dependent Claim
30 words
An array according to the any of the preceding claims, characterized in that said first bit lines (2) define source lines and said second bit lines (3) define drain lines.
Claim 5
Dependent Claim
19 words
An array according to any of the preceding claims, characterized in that said second bit lines (3) comprise silicide.
Claim 6
Dependent Claim
44 words
An array according to any of the preceding claims, characterized by isolation regions (8) of said first conductivity type, said isolation regions (8) being accommodated in said semiconductor material body (1) and being delimited between said bit lines (2,3) and said word lines (7).
Claim 7
Dependent Claim
170 words
In semiconductor material body having a first conductivity type and defining a main surface, a method for manufacturing an EPROM memory array with crosspoint configuration, characterized by the steps of: - forming a plurality of first buried bit lines having a second conductivity type and extending parallel to each other in said semiconductor body, - forming a plurality of insulation material regions extending on said first buried bit lines and partially in said semiconductor material body, - forming a plurality of second bit lines extending in said semiconductor material body up to said main surface thereof parallel to and between adjacent pairs of said first buried bit lines, - forming floating gate regions above said main surface of said semiconductor material body and in part on said insulation material regions perpendicular to said first and second bit lines and between two adjacent first and second bit lines, and - forming word lines extending perpendicular to said first and second bit lines above and electrically insulated from said floating gate regions.
Claim 8
Dependent Claim
170 words
In semiconductor material body having a first conductivity type and defining a main surface, a method for manufacturing an EPROM memory array with crosspoint configuration, characterized by the steps of: - forming a plurality of first buried bit lines having a second conductivity type and extending parallel to each other in said semiconductor body, - forming a plurality of insulation material regions extending on said first buried bit lines and partially in said semiconductor material body, - forming a plurality of second bit lines extending in said semiconductor material body up to said main surface thereof parallel to and between adjacent pairs of said first buried bit lines, - forming floating gate regions above said main surface of said semiconductor material body and in part on said insulation material regions perpendicular to said first and second bit lines and between two adjacent first and second bit lines, and - forming word lines extending perpendicular to said first and second bit lines above and electrically insulated from said floating gate regions.
Claim 9
Dependent Claim
198 words
A method according to claim 6, characterized by the steps of: - selectively introducing, in said semiconductor material body first doping ion species with a second conductivity type opposite to the first conductivity type, for defining the first buried bit lines; - forming insulation material regions above said first bit lines and at least partially inside said semiconductor material body; - depositing and shaping a first semiconductor material layer on said main surface for forming the floating gate regions, said first semiconductor material layer having windows facing selective portions of said main surface of said semiconductor material body; - selectively introducing second doping ion species having said second conductivity type into said semiconductor material body through said windows, for defining the second unburied bit lines; - depositing an insulating layer above said first semiconductor material layer and above said semiconductor material body at said windows; - depositing and shaping a second semiconductor material layer above said insulating layer for forming word lines which are perpendicular to said bit lines; and - introducing third doping ion species having said first conductivity type into said semiconductor material body for forming isolation regions between said word lines and said bit lines.
Claim 10
Dependent Claim
48 words
A method according to claim 7, characterized in that before introducing second doping ion species for defining said second unburied bit lines, fourth doping ion species having said first conductivity type are selectively introduced to form enriched regions in said semiconductor material body around said unburied bit lines.
Claim 11
Independent Claim
39 words
A method according to any of the preceding claims 6-7, characterized by a siliciding step after introducing fourth doping ion species for forming said enriched regions and before introducing second doping ion species for defining said second bit lines.
References Cited (Backward Citations)
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